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| 1/3 not for new design january 2002 this is information on a product still in production but not recommended for new designs. psd4xx zpsd4xx low cost field programmable microcontroller peripherals features summary single supply voltage: C 5 v10% for psd4xx C 2.7 to 5.5 v for psd4xx-v up to 1 mbit of uv eprom up to 16 kbit sram input latches programmable i/o ports page logic programmable security figure 1. packages pldcc68 (j) cldcc68 (l) tqfp68 (u) obsolete product(s) - obsolete product(s)
i psd4xx family psd4xx/zpsd4xx field-programmable microcontroller peripherals table of contents 1 introduction .................................................................................................................. .........................................1 2 key features .................................................................................................................. ......................................2 3 notation ...................................................................................................................... ..........................................3 4 zero-power background ......................................................................................................... ..............................3 5 integrated power management tm operation ........................................................................................................5 6 design flow ................................................................................................................... .......................................6 7 psd4xx family ................................................................................................................. ...................................7 8 table 2. psd4xx pin descriptions............................................................................................. .........................8 9 the psd4xx architecture ....................................................................................................... ...........................10 9.1 the zpld block.............................................................................................................. ............................10 9.1.1 the psd4xxa1 zpld block................................................................................................... .........10 9.1.1.1 the dpld ................................................................................................................ ..........12 9.1.1.2 the gpld ................................................................................................................ ..........13 9.1.1.3 tpa macrocell structure ................................................................................................ ...13 9.1.1.4 port b macrocell structure .............................................................................................. ...17 9.1.1.5 the zpld power management..........................................................................................18 9.1.2 the psd4xxa2 zpld block................................................................................................... .........22 9.1.2.1 the dpld ................................................................................................................ ..........24 9.1.2.2 the gpld ................................................................................................................ ..........26 9.1.2.3 port a macrocell structure .............................................................................................. ...26 9.1.2.4 port b macrocell structure .............................................................................................. ...30 9.1.2.5 port e macrocell structure .............................................................................................. ...33 9.1.2.6 the zpld power management..........................................................................................34 9.2 bus interface............................................................................................................... ................................37 9.2.1 bus interface configuration ............................................................................................... ...............37 9.2.2 psd4xx interface to a multiplexed bus ..................................................................................... ......38 9.2.3 psd4xx interface to non-multiplexed bus ................................................................................... ...38 9.2.4 data byte enable.......................................................................................................... ....................42 9.2.5 optional features ......................................................................................................... ....................43 9.2.6 bus interface examples.................................................................................................... ................43 9.3 i/o ports................................................................................................................... ...................................48 9.3.1 standard mcu i/o .......................................................................................................... ..................48 9.3.2 pld i/o ................................................................................................................... ........................48 9.3.3 address out............................................................................................................... .......................49 9.3.4 address in ................................................................................................................ ........................49 9.3.5 data port ................................................................................................................. .........................49 9.3.6 alternate function in ..................................................................................................... ...................49 9.3.7 peripheral i/o ............................................................................................................ .......................50 9.3.8 open drain outputs........................................................................................................ ..................50 9.3.9 port registers............................................................................................................ .......................51 9.3.10 port a ?functionality and structure..................................................................................... ............54 9.3.11 port b ?functionality and structure..................................................................................... ............54 9.3.12 port c and port d ?functionality and structure .......................................................................... ....57 9.3.13 port e ?functionality and structure..................................................................................... ............57 9.4 memory block ................................................................................................................ .............................61 9.4.1 eprom ..................................................................................................................... .......................61 9.4.2 sram ...................................................................................................................... .........................61 obsolete product(s) - obsolete product(s) ii psd4xx family psd4xx/zpsd4xx field-programmable microcontroller peripherals table of contents (cont.) 9.4.3 memory select map......................................................................................................... .................61 9.4.4 memory select map for 8031 application.................................................................................... .....62 9.4.5 peripheral i/o ............................................................................................................ .......................65 9.5 power management unit ....................................................................................................... .....................67 9.5.1 standby mode .............................................................................................................. ....................67 9.5.2 other power saving options ................................................................................................ ............70 10.0 page register .............................................................................................................. .......................................72 11.0 security protection........................................................................................................ ......................................72 12.0 system configuration ....................................................................................................... ..................................73 12.1 reset input ................................................................................................................ ..............................76 12.2 zpld and memory during reset............................................................................................... ..............76 12.3 register values during and after reset..................................................................................... .............76 12.4 zpld macrocell initialization .............................................................................................. .....................76 13.0 specifications............................................................................................................. .........................................77 13.1 absolute maximum ratings ................................................................................................... ..................77 13.2 operating range ............................................................................................................ .........................77 13.3 recommended operating conditions........................................................................................... ...........77 13.4 ac/dc parameters ........................................................................................................... .......................78 13.5 example of zpsd4xx typical power calculation at v cc = 5.0 v...........................................................80 13.6 dc characteristics (5 v 10% versions) ...................................................................................... ..........81 13.7 ac/dc parameters ?zpld timing parameters .................................................................................. ...82 13.8 microcontroller interface ?ac/dc parameters ............................................................................... ........84 13.9 dc characteristics (zpsd4xxv versions) (3.0 v 10% versions) ........................................................88 13.10 ac/dc parameters ?zpld timing parameters (3.0 v 10% versions)................................................89 13.11 microcontroller interface ?ac/dc parameters (3.0 v 10% versions)...................................................91 14.0 timing diagrams............................................................................................................ .....................................95 15.0 pin capacitance............................................................................................................ ....................................102 16.0 ac testing ................................................................................................................. .......................................102 17.0 erasure and programming.................................................................................................... ............................102 18.0 psd4xx pin assignments ..................................................................................................... ...........................103 19.0 package information ........................................................................................................ .................................105 20.0 psd4xx product ordering information ........................................................................................ ....................110 20.1 psd4xx family ?selector guide ............................................................................................. ............110 20.2 part number construction ................................................................................................... ..................111 20.3 ordering information....................................................................................................... .......................111 obsolete product(s) - obsolete product(s) 1 1.0 introduction programmable peripheral psd4xx family field-programmable microcontroller peripherals the psd4xx family is a microcontroller peripheral that integrates high-performance and user-configurable blocks of eprom, programmable logic, and sram into one part. the psd4xx products also provide a powerful microcontroller interface that eliminates the need for external ?lue logic? the no ?lue logic?concept provides a user-programmable interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that is easy to use. the part s integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller. the psd4xx provides two zero-power plds (zpld): a decode pld (dpld) and a general-purpose pld (gpld). a configuration bit (turbo) can be set by the mcu, and will automatically place the zplds into standby mode if no inputs are changing. the zplds are designed to consume minimum power using zero-power cmos technology that uses only 10 ? (typical) standby current. unused product terms are automatically disabled, also reducing power, regardless of the turbo bit setting. the main function of the dpld is to perform address decoding for the internal i/o ports, eprom, and sram. the address decoding can be based on up to 24 bits of address inputs, control signals (rd, wr, psen, etc.), and internal page logic. the dpld supports separate program and data spaces (for 8031 compatible mcus). the general-purpose pld (gpld) can be used to implement various logic functions defined by the user, such as: state machines loadable counters and shift registers inter-processor mailbox external control logic (chip selects, output enables, etc.). the gpld has access to up to 59 inputs, 118 product terms, 24 macrocells, and 24 i/o pins. obsolete product(s) - obsolete product(s) psd4xx family 2 1.0 introduction (cont.) the psd4xx has 40 i/o pins that are divided among 5 ports. each i/o pin can be individually configured to provide many functions, including the following: mcu i/o gpld i/o latched address output (for mcus with multiplexed data bus) data bus (for mcus with non-multiplexed data bus). the psd4xx can easily interface with virtually any 8- or 16-bit microcontroller with a multiplexed or non-multiplexed bus. all of the mcu control signals are connected to the zplds, enabling the user to generate signals for external devices. the psd4xx provides between 256 kbits and 1 mbit of eprom that is divided in to four equal-sized blocks. each block can occupy a different address location, allowing for versatile address mapping. the access time of the eprom includes the address latching and dpld decoding. the psd4xx has an optional 16 kbit sram that can be battery-backed by connecting a battery to the vstby pin. the battery will protect the contents of the sram in the event of a power failure. therefore, you can place data in the sram that you want to keep after the power is switched off. power switchover to the battery automatically occurs when v cc drops below v stby . a four-bit page register enables easy access to the i/o section, eprom, and sram for microcontrollers with limited address space. the page register outputs are connected to both zplds and thus can also be used for external paging schemes. the power management unit (pmu) of the psd4xx enables the user to control the power consumption on selected functional blocks, based on system requirements. for microcontrollers that do not generate a chip select input for the psd, the automatic power-down (apd) unit of the pmu can be setup to enable the psd to enter power down mode or sleep mode, based on the inactivity of ale (or as). implementing your design has never been easier than with psdsoft st s software development suite. using psdsoft, you can do the following: configure your psd4xx to work with virtually any microcontroller specify what you want implemented in the programmable logic using a design file simulate your design download your design to the part using a programmer. 2.0 key features o single-chip programmable peripheral for microcontroller-based applications o 256k to 1 mbit of uv eprom with the following features: configurable as 32, 64, or 128 k x 8; or as 16, 32, or 64 k x 16 divided into four equally-sized mappable blocks for optimized address mapping as fast as 70 ns access time, which includes address decoding built-in zero-power technology o 16 kbit sram is configurable as 2k x 8 or 1k x 16. the access time can be as quick as 70 ns, including address decoding. the contents of the sram can be battery-backed by connecting a battery to the vstby pin. the sram also has built-in zero-power technology. o 40 i/o pins (divided into five 8-bit ports) that can be individually configured for: standard mcu i/o pld/macrocell i/o latched address output high-order address inputs special function i/o open-drain output obsolete product(s) - obsolete product(s) psd4xx family 3 2.0 key features o two zero-power programmable logic devices (zplds): the decode pld (dpld) and the general-purpose pld (gpld) can be used for: up to 59 input and 126 output product terms 24 macrocells and i/o decode up to 16 mb of address state machines and state logic generate external signals (chip selects, bus interface, etc.) o microcontroller logic that eliminates the need for external ?lue logic?has the following features: ability to interface to multiplexed and non-multiplexed buses built-in address latches for multiplexed address/data bus ale and reset polarity are programmable multiple configurations are possible for interface to many different microcontrollers o page logic is connected to the zplds and expands the mcu address space to up to 16 times o programmable power management allows: sram, eprom, and zplds to enter standby mode automatically disabling of the clock input to the zplds zplds to enter a special low power mode (sleep mode), based on turbo bit setting o a security bit prevents reading the psd4xx configuration and the zpld contents. setting this bit will prevent the device from being copied on a device programmer. o built-in security enables the user to block read accesses from a device programmer o package choices include 68-pin plcc, 68-pin cldcc, and 80-pin tqfp o programmable polarity reset output (includes hysteresis), based on reset input o simple, menu-driven software (psdsoft) allows configuration and design entry on a pc. 3.0 notation throughout this data sheet, references are made to the psd4xx. in most cases, these references also cover the zpsd4xx and zpsd4xxv products. exceptions will be noted. the main difference between the zpsd4xx and the psd4xx is the standby current (isb). the zpsd4xx devices have been rated for a lower standby current. also, there is no low-voltage version of the psd4xx. there is only the low-voltage version of the zpsd4xx, which has a v suffix. portable and battery powered systems have recently become major embedded control application segments. as a result, the demand for electronic components having extremely low power consumption has increased dramatically. recognizing this need, st has developed a new zero power technology. psd4xx products virtually eliminate the dc component of power consumption reducing it to standby levels. eliminating the dc component is the basis for the words ?ero power? psd4xx products also minimize the ac power component when the chip is changing states. the result is a programmable microcontroller peripheral family that replaces discrete circuit functions while drawing minimal current. 4.0 zero-power background obsolete product(s) - obsolete product(s) psd4xx family 4 prog. bus intrf adio port prog. port prog. port port c prog. port port d control rd, wr ad0 ?ad15 pc0 ?pc7 pd0 ?pd7 clkin clkin page reg. zpld input bus global config. & security port a power manager unit vstdby pa0 ?pa7 prog. port port b pb0 ?pb7 prog. port port e pe0 ?pe7 address/data/control bus port a macrocells port b macrocells port e macrocells (note 2) 27pt (note 1) (note 1) 80pt 11pt clkin 256k 1m bit eprom 16 k bits sram i/o decoder eprom selects sram select peripheral selects macrocell feedback or port input csiop general pld (gpld) 24 macrocells decode pld (dpld) notes: 1. zpld input bus ? a1 = 36 + clock = 37 inputs ? a2 = 58 + clock = 59 inputs 2. port e macrocells available on a2 versions only. figure 1. psd4xx block diagram obsolete product(s) - obsolete product(s) - obsolet psd4xx family 5 5.0 integrated power management tm operation upon each address or logic input change to the zpsd, the device powers up from low power standby for a short time. then the zpsd consumes only the necessary power to deliver new logic or memory data to its outputs as a response to the input change. after the new outputs are stable, the zpsd latches them and automatically reverts back to standby mode. the i cc current flowing during standby mode and during dc operation is identical and is only a few microamperes. the zpsd automatically reduces its dc current drain to these low levels and does not require controlling by the csi (chip select input). disabling the csi pin unconditionally forces the zpsd to standby mode independent of other input transitions. the only significant power consumption in the zpsd occurs during ac operation. the zpsd contains the first architecture to apply zero power techniques to memory and logic blocks. figure 2 compares zpsd zero-power operation to the operation of a discrete solution. a standard microcontroller (mcu) bus cycle usually starts with an ale (or as) pulse and the generation of an address. the zpsd detects the address transition and powers up for a short time. the zpsd then latches the outputs of the pad, eprom and sram to the new values. after finishing these operations, the zpsd shuts off its internal power, entering standby mode. the time taken for the entire cycle is less than the zpsd s ?ccess time. the zpsd will stay in standby mode if inputs do not change between bus cycles. in an alternate system implementation using discrete eprom, sram, and other discrete components, the system will consume operating power during the entire bus cycle. this is because the chip select inputs on the memory devices are usually active throughout the entire cycle. the ac power consumption of the zpld may be calculated using the composite frequency of the mcu address and control signals, as well as any other logic inputs to the zpld. note: the zpsd4xx is rated for lower standby current (i sb ) than the psd4xx. ale discrete eprom, sram & logic address eprom access sram access eprom access i cc zpsd zpsd zpsd time figure 2. zero-power operation vs. discrete implementation obsolete product(s) - obsolete product(s) psd4xx family 6 figure 3. psdsoft development tools psdsilos iii silosiii chip simulation psd programmer psdpro/magicpro chip programming psd compiler (zpld fitting, address translation) psdabel zpld description (state machine, decoding) psdsoft development software psd configuration chip configuration third party programmers code file shown in figure 3 (below) is the software design flow for a psd4xx device. psdsoft st s software development suite is used throughout the design phase. you start with a design file that is written in psdabel? high-level hardware description language (hdl). before you compile your design, you must also configure the psd4xx so it knows what signals to expect from your microprocessor and what pre-runtime options should be set (such as the security bit). once you have a design file and have configured the device, you are ready to run the fitter and address translator. the fitter accepts input from psdabel and psd configuration, synthesizes this user logic and configuration, and fits the design to the psd silicon. the address translator process allows the user to map the mcu firmware from a cross- compiler (in intel hex or s-record format) into the nvm memory blocks within the psd. as a result, the mcu firmware is merged with the logic and configuration definition of the psd. the output of the address translator and the fitter is the required object file that is used by a programmer to program the psd device. the object file includes chip configuration, the pld fusemap, and mcu firmware information. psdsilosiii is an optional program that provides functional chip-level simulation of the psd4xx. psdsoft automatically creates files for input to the simulator. these files convey relevant design information to the simulator. as a result, the user only has to create a stimulus file since all of the signals and node names are taken from the design file. 6.0 design flow obsolete product(s) - obsolete product(s) psd4xx family 7 7.0 psd4xx family there are 12 unique devices in the psd4xx family. the part classifications are based on zpld configuration and size, eprom size, and data bus width. the features of each part are listed in table 1. see the ordering information section at the end of this document. part bus dpld + gpld i/o pmu eprom sram # bit inputs product registered pins k bit k bit terms macrocells 401a1 x8/x16 37 113 8 40 yes 256 16 411a1 x8 37 113 8 40 yes 256 16 402a1 x8/x16 37 113 8 40 yes 512 16 412a0 x8 37 113 8 40 yes 512 412a1 x8 37 113 8 40 yes 512 16 403a1 x8/x16 37 113 8 40 yes 1024 16 413a1 x8 37 113 8 40 yes 1024 16 401a2 x8/x16 59 126 24 40 yes 256 16 411a2 x8 59 126 24 40 yes 256 16 402a2 x8/x16 59 126 24 40 yes 512 16 412a2 x8 59 126 24 40 yes 512 16 403a2 x8/x16 59 126 24 40 yes 1024 16 413a2 x8 59 126 24 40 yes 1024 16 table 1. psd4xx product matrix note: pmu = power management unit. obsolete product(s) - obsolete product(s) psd4xx family 8 pin name pin function type function descriptions adio0 ?adio15 address/data bus i/o 1. address/data bus, multiplexed bus mode 2. address bus, non-multiplexed bus mode rd multiple names i multiple functions 1. read 1. read signal 2. e 2. e signal (clock) 3. ds 3. data strobe signal 4. lds 4. low byte data strobe wr multiple names i multiple functions 1. wr 1. write signal 2. r/w 2. read-write signal 3. wrl 3. low byte write signal csi chip select input i active low, select psd4xx standby mode if high. reset reset input i reset i/o ports, zpld/macrocells, and configuration registers. active low. clkin input clock i clock input to zpld macrocells, zpld array and apd counter. connect to ground if clock input not used. pa0 ?pa7 i/o port a i/o multiple functions 1. i/o port 2. zpld/macrocell i/o port 3. latched address outputs (pa0 ?pa7) ? (a0 ?a7) 4. high address inputs (a16 ?a23) pb0 ?pb7 i/o port b i/o multiple functions 1. i/o port 2. zpld/macrocell i/o port 3. latched address outputs (pb0?b7) ? (a0 a7) or (a8?15) pc0 ?pc7 i/o port c i/o multiple functions cmos 1. i/o port or 2. zpld input port * od 3. latched address outputs (pc0 ?pc7) ? (a0 a7) 4. data port (d0 ?d7, non-multiplexed bus) pd0 ?pd7 i/o port d i/o multiple functions cmos 1. i/o port or 2. zpld input port * od 3. latched address outputs (pd0?d7) ? (a0 a7) or (a8?15) 4. data port (d8 d15, non-multiplexed bus) 8.0 table 2. psd4xx pin descriptions the following table describes the pin names and pin functions of the psd4xx. pins that have multiple names and/or functions are defined by user configuration. * available only in psd4xxa2 and zpsd4xxa2 series. obsolete product(s) - obsolete product(s) psd4xx family 9 pin name pin function type function descriptions pe0 port pe, pin 0 i/o multiple functions 1. bhe 1. high byte enable, 16 bit data 2. psen 2. read program memory, 8031 signal 3. wrh 3. write high data byte 4. uds 4. upper data strobe 5. siz0 5. byte enable, 68300 signal 6. pe0 6. i/o pin 7. pe0 7. zpld i/o pin 8. pe0 8. latched address out ?a0 pe1 port pe, pin 1 i/o multiple functions 1. ale 1. address strobe 2. pe1 2. i/o pin 3. pe1 3. zpld i/o pin 4. pe1 4. latched address out ?a1 pe2 port pe, pin 2 multiple functions 1. pe2 i/o 1. i/o pin 2. pe2 2. zpld i/o pin * 3. pe2 3. latched address out ?a2 pe3 port pe, pin 3 multiple functions 1. pe3 i/o 1. i/o pin 2. pe3 2. zpld i/o pin * 3. pe3 3. latched address out ?a3 pe4 port pe, pin 4 multiple functions 1. pe4 i/o 1. i/o pin 2. pe4 2. zpld i/o pin * 3. pe4 3. latched address out ?a4 pe5 port pe, pin 5 multiple functions 1. pe5 i/o 1. i/o pin 2. pe5 2. zpld i/o pin * 3. pe5 3. latched address out ?a5 pe6 port pe, pin 6 multiple functions 1. pe6 i/o 1. i/o pin 2. pe6 2. zpld i/o pin * 3. pe6 3. latched address out ?a6 pe7 port pe, pin 7 multiple functions 1. apd clk 1. automatic power down clock input 2. pe7 i/o 2. i/o pin 3. pe7 3. zpld i/o pin * 4. pe7 4. latched address out ?a7 vstdby vstdby i sram power pin for standby operation (battery backup) v cc v cc iv cc power pin gnd gnd i ground pin 8.0 table 2. psd4xx pin descriptions (cont.) * available only in psd4xxa2 and zpsd4xxa2 series. obsolete product(s) - obsolete product(s) psd4xx family 10 9.0 the psd4xx architecture psd4xx consists of five major functional blocks: o zpld blocks o bus interface o i/o ports o memory block o power management unit the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. the chip configurations are specified by the user in the psdsoft development software. other configurations are specified by setting up the appropriate bits in the configuration registers during run time. 9.1 the zpld block the psd4xx series devices provide two zpld configurations. the zpld in the psd4xxa1 devices has 8 registered macrocells, 8 combinatorial macrocells, and up to 113 product terms. the psd4xxa2 has a full function zpld with 24 registered macrocells and up to 126 product terms. 9.1.1 the psd4xxa1 zpld block key features o 2 embedded zpld devices o 8 registered and 8 combinatorial macrocells o combinatorial/registered outputs o maximum 113 product terms o programmable output polarity o user configured register clear/preset o user configured register clock input o 37 inputs o accessible via 16 i/o pins o power saving mode o uv-erasable general description the zpld block has 2 embedded pld devices: o dpld the address decoding pld, generating select signals to internal i/o or memory blocks. o gpld the general purpose pld provides 8 registered and combinatorial programmable macrocells for general or complex logic implementation; dedicated to user application. figure 4 shows the architecture of the zpld. the pld devices all share the same input bus. the true or complement of the 37 input signals are fed to the programmable and-array. names and sources of the input signals are shown in table 3. the pb signals, depending on user configuration, can either be macrocell feedbacks or inputs from port b. obsolete product(s) - obsolete product(s) psd4xx family 11 figure 4. zpld block diagram page reg. adio port pmu csi rd/ e/ds pe1 (psen/bhe) pe0 (ale/as) wr / r_w reset clkin pgr0 ?3 a8 ?a15 a0, a1 and array and array dpld es0 ?es3 rs0 csiop psel0 ?psel1 8 i /o macrocells pa 8 i /o macrocells pb (note 1) 80 pt pb0 ?pb7 pa0 ?pa7 prog. port port a prog. port port b dpld gpld zpld input bus (decoding pld) (general purpose pld) note 1: a1 = 25 pt on port a a2 = 27 pt on port a the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 12 signal name from pa0 ?pa7 port a inputs or macrocell pa feedback pb0 ?pb7 port b inputs or macrocell pb feedback pe0 ?pe1 port e inputs (signals ale, psen/bhe) pgr0 ?pgr3 page mode register a8 ?a15, a0, a1 mcu address lines rd/e/ds mcu bus signal wr/r_w mcu bus signal clkin input clock reset reset input csi csi input (ored with power down from pmu) table 3. zpld input signals 9.0 the psd4xx architecture (cont.) 9.1.1.1 the dpld the dpld is used for internal address decoding generating the following eight chip select signals: o es0 ?es3 eprom selects, block 0 to block 3 o rs0 sram block select o csiop i/o decoder chip select o psel0 ?psel1 peripheral i/o mode select signals the i/o decoder enabled by the csiop generates chip selects for on-chip registers or i/o ports based on address inputs a[7:0]. as shown in figure 4, the dpld consists of a large programmable and array. there are a total of 37 inputs and 8 outputs. each output consists of a single product term. although the user can generate select signals from any of the inputs, the select signals are typically a function of the address and page register inputs. the select signals are defined by the user in the abel file (psdabel). the address line inputs to the dpld include a0, a1 and a8 ?a15. if more address lines are needed, the user can bring in the lines through port a to the dpld. obsolete product(s) - obsolete product(s) psd4xx family 13 9.1.1.2 the gpld the structure of the general purpose pld consists of a programmable and array and 2 sets of i/o macrocells. the array has 37 input signals, same as the dpld. from these inputs, ?nded?functions are generated as product term inputs to the macrocells. the i/o macrocell sets are named after the i/o ports they are linked to, e.g., the macrocells connected to port b are named pb macrocells. the pb macrocells are registered macrocells with d-type flip-flops, where pa consists of combinatorial macrocells. 9.1.1.3 tpa macrocell structure figure 5 shows the pa macrocell block, which consists of 8 identical combinatorial macrocells. each macrocell output can be connected to its own i/o pin on port a. there is one user programmable global product term that is output from the gpld s and array which is shared by all the macrocells in port a: o pa.oe enable or tri-state port a output pins the circuit of a pa macrocell is shown in figure 6. there are 4 product terms from the gpld s and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o gpld input use port a pin as dedicated input o gpld output use port a pin as dedicated output 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 14 figure 5. dpld logic array pa0 ?pa7 (8) (8) (2) (10) (3) (1) (1) (inputs) pb0 ?pb7 pe0 ?pe1 (4) pgr0 ?pgr3 a8 ?a15, a0, a1 csi, clkin reset rd/e/ds wr /r_w es0 es1 es2 es3 rs0 csiop psel0 psel1 4 eprom block selects ram select i /o decoder select peripheral i /o selects dpld inputs = 37 dpld outputs = 8 (ale, psen/bhe) 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 15 figure 6. pa macrocell block diagram and array mc0 pa0 mc1 pa1 mc7 pa7 macro. out pa0 input macro. out pa1 input macro. out pa7 input pt [ 2:0 ] pa0 pt [ 2:0 ] pa1 pt [ 2:0 ] pa7 pa.oe port a i/o cells pa macrocell zpld bus 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 16 figure 7. pa macrocell pt pt pt pt and array polarity select pld in select mux pa .oe pt0 pt1 pt2 pai note: i = 7 to 0 macro . out i/o pin pai port a internal address/data bus pai input zpld bus 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 17 9.1.1.4 port b macrocell structure figure 7 shows the pb macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port b. the two inputs, clkin and macro-rst, are used as clock and clear inputs to all the macrocells. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pb macrocell is shown in figure 8. there are 10 product terms from the gplds and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop. o combinatorial output select output from or gate. o gpld input use port b pin as dedicated input. o gpld output use port b pin as dedicated output. o gpld i/o use port b pin as bidirectional pin. o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port b pin, port b can be configured to perform other user defined i/o functions. each d flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. the signals are defined as follow: o preset active only if defined by a product term (pbi.pr) o clear two selectable inputs: reset input and/or user defined product term (pbi.re) o clk two selectable inputs ? clkin input or user defined product term (pbi.clk). the macrocell is operated in synchronous mode if the clock input is clkin, and is in asynchronous mode if the clock is a product-term clock defined by the user. figure 9 shows the input/output path of a pb macrocell to the port pin with which it is associated. if the port pin is specified as a pb output pin in the psdsoft, the mux in the i/o port cell selects the pb macrocell as an output of the port pin. the output enable signal to the buffer in the i/o cell can be controlled by a product term from the and array. if the port pin is specified as a zpld input pin, the mux in the pb macrocell selects the port input signal to be one of the 61 signals in the zpld input bus. 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 18 9.0 the psd4xx architecture (cont.) 9.1.1.5 the zpld power management the zpld implements a zero power mode, which provides considerable power savings for low to medium frequency operations. to enable this feature, the zpld turbo bit in the power management mode register 0 (pmmr0) has to be turned off. if none of the inputs to the zpld are switching for a time period of 90ns, the zpld puts itself into zero power mode and the current consumption is minimal. the zpld will resume normal operation as soon as one or more of the inputs change state. two other features of the zpld provide additional power savings: 1. clock disable: users can disable the clock input to the zpld and/or macrocells,thereby reducing ac power consumption. 2. product term disable: unused product terms in the zpld are disabled by the psdsoft software automatically for further power savings. the zpld power configuration is described in the power management unit section. obsolete product(s) - obsolete product(s) psd4xx family 19 figure 8. pb macrocell block diagram and array macro .out pb0 .oe pb0 ?input macro .out pb1 .oe pb1 input macro .out pb7 .oe pb7?input ptb0 ? [ 0 . . 5 ] pb0 .pr pb0 .re pb0 .oe pb0 .clk pb0 ptb1 ? [ 0 . . 5 ] pb1 .pr pb1 .re pb1 .oe pb1 .clk pb1 ptb7 ? [ 0 . . 5 ] pb7 .pr pb7 .re pb7 .oe pb7 .clk pb7 clkin macro ?rst port b i/o cells pb macrocell mc0 mc1 mc7 pb0 pb1 pb7 zpld bus 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 20 figure 9. pb macrocell dq pt pt pt pt pt pt pt pt pt pt and array polarity select comb /reg select c pr mux pld?n select mux clk select mux pbi pbi .oe pbi .pr pt0 pt1 pt2 pt3 pt4 pt5 pbi .clk pbi .re macro rst clkin macro . out i /o pin pbi port b internal address /data bus pbi ?input zpld bus 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 21 figure 10. pb macrocell input/output port dq psd4xx fig. 5 and array pt polarity select cl ck pr control clk select mux pt clock pt output enable (oe) pt reset pts pt clear macro_rst global clock port pin comb./reg. select gpld macrocell output mux mux mux pcr dq wr direction register dq wr d g q ale pdr port input input output address a[0-7] or a[8-15] gpld output gpld macrocell i/o port cell internal address/data/control bus zpld input bus clkin 9.0 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 22 the psd4xx architecture (cont.) 9.1.2 the psd4xxa2 zpld block key features o 2 embedded zpld devices o 24 macrocells o combinatorial/registered outputs o maximum 126 product terms o programmable output polarity o user configured register clear/preset o user configured register clock input o 59 inputs o accessible via 24 i/o pins o power saving mode o uv-erasable general description the zpld block has 2 embedded pld devices: o dpld the address decoding pld, generating select signals to internal i/o or memory blocks. o gpld the general purpose pld provides 24 programmable macrocells for general or complex logic implementation; dedicated to user application. figure 11 shows the architecture of the zpld. the pld devices all share the same input bus. the true or complement of the 59 input signals are fed to the programmable and-array. names and source of the input signals are shown in table 4. the pa, pb, pe signals, depending on user configuration, can either be macrocell feedbacks or inputs from port a, b or e. obsolete product(s) - obsolete product(s) psd4xx family 23 page reg. adio port prog. port port c prog. port port d pmu csi rd/ e/ds wr / r_w reset clkin pgr0 ?3 a8 ?a15 a0, a1 pc0 ?pc7 pd0 ?pd7 and array and array and array dpld es0 ?es3 rs0 csiop psel0 ?psel1 8 i /o macrocells pa 8 i /o macrocells pb 8 i /o macrocells pe 27 pt 80 pt 11 pt pe0 ?pe7 pb0 ?pb7 pa0 ?pa7 prog. port port a prog. port port b prog. port port e dpld gpld zpld input bus (decoding pld) (general purpose pld) the psd4xx architecture (cont.) figure 11. psd4xxa2 zpld block diagram obsolete product(s) - obsolete product(s) signal name from pa0 ?pa7 port a inputs or macrocell pa feedback pb0 ?pb7 port b inputs or macrocell pb feedback pe0 ?pe7 port e inputs or macrocell pe feedback pc0 ?pc7 port c inputs pd0 ?pd7 port d inputs pgr0 ?pgr3 page mode register a8 ?a15, a0, a1 mcu address lines rd/e/ds mcu bus signal wr/r_w mcu bus signal clkin input clock reset reset input csi csi input (ored with power down from pmu) psd4xx family 24 table 4. zpld input signals the psd4xx architecture (cont.) 9.1.2.1 the dpld the dpld is used for internal address decoding generating the following eight chip select signals: o es0 ?es3 eprom selects, block 0 to block 3 o rs0 sram block select o csiop i/o decoder chip select o psel0 ?psel1 peripheral i/o mode select signals the i/o decoder enabled by the csiop generates chip selects for on-chip registers or i/o ports based on address inputs a[7:0]. as shown in figure 12, the dpld consists of a large programmable and array. there are a total of 59 inputs and 8 outputs. each output consists of a single product term. although the user can generate select signals from any of the inputs, the select signals are typically a function of the address and page register inputs. the select signals are defined by the user in the abel file (psdabel). the address line inputs to the dpld include a0, a1 and a8 ?a15. if more address lines are needed, the user can bring in the lines through port a to the dpld. obsolete product(s) - obsolete product(s) psd4xx family 25 figure 12. dpld logic array pa0 ?pa7 (8) (8) (8) (8) (8) (4) (10) (3) (1) (1) (inputs) pb0 ?pb7 pe0 ?pe7 pc0 ?pc7 pd0 ?pd7 pgr0 ?pgr3 a8 ?a15, a0, a1 csi, clkin reset rd/e/ds wr /r_w es0 es1 es2 es3 rs0 csiop psel0 psel1 4 eprom block selects ram select i /o decoder select peripheral i /o selects dpld inputs : 59 dpld outputs : 8 the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 26 the psd4xx architecture (cont.) 9.1.2.2 the gpld the structure of the general purpose pld consists of a programmable and array and 3 sets of i/o macrocells. the array has 59 input signals, same as the dpld. from these inputs, ?nded?functions are generated as product term inputs to the macrocells. the i/o macrocell sets are named after the i/o ports they are linked to, e.g., the macrocells connected to port a are named pa macrocells. the 3 sets of macrocells, pa, pb and pe, are similar in structure and function. figure 13 shows the output/input path of a gpld macrocell to the port pin with which it is associated. if the port pin is specified as a gpld output pin in psdsoft, the mux in the i/o port cell selects the gpld macrocell as an output of the port pin. the output enable signal to the buffer in the i/o cell can be controlled by a product term from the and array. if the port pin is specified as a zpld input pin, the mux in the gpld macrocell selects the port input signal to be one of the 61 signals in the zpld input bus. 9.1.2.3 port a macrocell structure figure 14 shows the pa macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port a. there are 3 user programmable global product terms output from the gpld s and array which are shared by all the macrocells in port a: o pa.oe enable or tri-state port a output pins o pa.pr preset d flip flop in the macrocells o pa.re reset/clear d flip flop in the macrocells two other inputs, clkin and macro-rst, are used as clock and clear inputs to the d flip flop. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pa macrocell is shown in figure 15. there are 6 product terms from the gpld s and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use port a pin as dedicated input o gpld output use port a pin as dedicated output o gpld i/o use port a pin as bidirectional pin o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port a pin, port a can be configured to perform other user defined i/o functions. the two global product terms assigned for asynchronous clear (pa.re) and preset (pa.pr) are mainly for proper pa macrocell initialization. the macrocell flip-flop can also be cleared during reset by macro-rst, if such an option is chosen. the clock source is always the input clock clkin. obsolete product(s) - obsolete product(s) psd4xx family 27 figure 13. gpld macrocell input/output port dq psd4xx fig. 18 and array pt polarity select cl ck pr control clk select mux pt clock pt output enable (oe) pt reset pts pt clear macro_rst global clock port pin comb./reg. select macrocell output mux mux mux pcr dq wr direction register dq wr d g q ale pdr port input input output address a[0-7] or a[8-15] gpld output latch qd latch only on port a gpld macrocell i/o port cell internal address/data/control bus zpld input bus obsolete product(s) - obsolete product(s) psd4xx family 28 figure 14. pa macrocell block diagram and array mc0 pa0 mc1 pa1 mc7 pa7 macro. out pa0 input macro. out pa1 input macro. out pa7 input pt [ 2:0 ] pa0 pt [ 2:0 ] pa1 pt [ 2:0 ] pa7 pa.pr pa.re pa.oe clkin macro rst port a i/o cells pa macrocell zpld bus the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 29 figure 15. psd4xxa2 pa macrocell dq pt pt pt pt pt pt and array polarity select pld in select c pr mux mux pa .oe pa.pr pt0 pt1 pt2 pa .re pai macro rst note: i = 7 to 0 clkin macro . out i/o pin pai port a comb / reg select internal address/data bus pai input zpld bus the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 30 the psd4xx architecture (cont.) 9.1.2.4 port b macrocell structure figure 16 shows the pb macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port b. the two inputs, clkin and macro-rst, are used as clock and clear inputs to all the macrocells. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pb macrocell is shown in figure 17. there are 10 product terms from the gpld s and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop. o combinatorial output select output from or gate. o gpld input use port b pin as dedicated input. o gpld output use port b pin as dedicated output. o gpld i/o use port b pin as bidirectional pin. o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port b pin, port b can be configured to perform other user defined i/o functions. each d flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. the signals are defined as follow: o preset active only if defined by a product term (pbx.pr) o clear two selectable inputs: reset input or user defined product term (pbx .re) o clk two selectable inputs ? clkin input or user defined product term (pbx.clk). the macrocell is operated in synchronous mode if the clock input is clkin, and is in asynchronous mode if the clock is a product-term clock defined by the user. obsolete product(s) - obsolete product(s) psd4xx family 31 figure 16. psd4xxa2 pb macrocell block diagram and array macro .out pb0 .oe pb0 ?input macro .out pb1 .oe pb1 input macro .out pb7 .oe pb7?input ptb0 ? [ 0 . . 5 ] pb0 .pr pb0 .re pb0 .oe pb0 .clk pb0 ptb1 ? [ 0 . . 5 ] pb1 .pr pb1 .re pb1 .oe pb1 .clk pb1 ptb7 ? [ 0 . . 5 ] pb7 .pr pb7 .re pb7 .oe pb7 .clk pb7 clkin macro ?rst port b i/o cells pb macrocell mc0 mc1 mc7 pb0 pb1 pb7 zpld bus the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 32 dq pt pt pt pt pt pt pt pt pt pt and array polarity select comb /reg select c pr mux pld?n select mux clk select mux pbi pbi .oe pbi .pr pt0 pt1 pt2 pt3 pt4 pt5 pbi .clk pbi .re macro rst clkin macro . out i /o pin pbi port b internal address /data bus pbi ?input note: i = 7 to 0 zpld bus figure 17. psd4xxa2 pb macrocell the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 33 9.1.2.5 port e macrocell structure figure 18 shows the pe macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port e. there are 3 user programmable global product terms output from the gpld s and array which are shared by all the macrocells in port e: o pe.oe enable or tri-state port pe output pins o pe.pr preset d flip flop in the macrocells o pe.re reset/clear d flip flop in the macrocells two other inputs, clkin and macro-rst, are used as clock and clear inputs to the d flip flop. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pe macrocell is shown in figure 19. there is only one product term from the gpld s and array as input to the macrocell. users can select the polarity of the output and configure the macrocell to operate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use port e pin as dedicated input o gpld output use port e pin as dedicated output o gpld i/o use port e pin as bidirectional pin o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to port e pin, port e can be configured to perform other user defined i/o functions. if pins pe0 and pe1 are used as bus control signal inputs (ale, psen/bhe), the corresponding macrocells' feedbacks are disabled. the bus control signals are connected to the zpld input bus. the two global product terms assigned for asynchronous clear (pe.re) and preset (pe.pr) are for proper pe macrocell initialization. the macrocell flip-flop can also be cleared during reset by macro-rst as an option. the clock source is always the input clock clkin. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 34 9.1.2.6 the zpld power management the zpld implements a zero power mode, which provides considerable power savings for low to medium frequency operations. to enable this feature, the zpld turbo bit in the power management mode register 0 (pmmr0) has to be turned off. if none of the inputs to the zpld are switching for a time period of 70ns, the zpld puts itself into zero power mode and the current consumption is minimal. the zpld will resume normal operation as soon as one or more of the inputs change state. two other features of the zpld provide additional power savings: 1. clock disable: users can disable the clock input to the zpld and/or macrocells, thereby reducing ac power consumption. 2. product term disable: unused product terms in the zpld are disabled by the psdsoft software automatically for further power savings. the zpld power configuration is described in the power management unit section. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 35 and array mc0 pe0 mc1 pe1 mc7 pe 7 macro .out pe0 ?input macro .out pe1 ?input macro .out pe7?input pt pe0 pt pe1 pt pe7 pe .pr pe .re pe .oe clkin macro ?rst port e i/o cells pe macrocell zpld bus figure 18. pe macrocell block diagram the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 36 figure 19. pe macrocell dq pt pt pt pt and array polarity select pld in select c pr mux mux pe .oe pe .pr pt pe .re pei macro rst note: i = 7 to 0 clkin macro .out i/o pin pei port e internal address/data bus pei input comb / reg select zpld bus the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) multiplexed data bus bus control microcontroller width signals mux 8 wr, rd, psen, a0 8031/80c51 mux/ non-mux 8/16 r/w, e, bhe, a0 68hc11 mux 8/16 wr, rd, bhe, a0 80c196/80c186 mux 16 wrl, rd, wrh, a0 80c196sp non-mux 16 r/w, lds, uds 68302 non-mux 8/16 r/w, ds, siz0, a0 68340 non-mux 16 r/w, ds, bhe, ble 68330, 68331 non-mux 8 rd, wr 68hc05c non-mux 16 r/w, e, lstrb, a0 68hc12 non-mux 16 r/w, ds 68hc16 psd4xx family 37 table 5. typical microcontroller bus types 9.2 bus interface the bus interface is very flexible and can be configured to interface to most microcontrollers with no glue logic. table 5 lists some of the bus types to which the bus interface is able to interface. 9.2.1 bus interface configuration the bus interface logic is user configurable. the type of bus interface is specified by the user in the psdsoft software (psd configuration). the bus control input pins have multi-function capabilities. by choosing the right configuration, the psd4xx is able to interface to most microcontrollers, including the ones listed in table 5. in table 6, the names of the bus control input signal pins and their multiple functions are shown. for example, pin pe0 can be configured by the psd configuration software to perform any one of the five functions. examples on the interface between the psd4xx and some typical microcontrollers are shown in following sections. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 38 psd4xx family pin pin pin pin pin pin name function function function function function 123 45 rd rd e ds lds wr wr r/w wrl pe0 bhe psen wrh uds siz0 pe1 ale ad0 a0 ble table 6. alternate pin functions 9.2.2 psd4xx interface to a multiplexed bus figure 20 shows a typical connection to a microcontroller with a multiplexed bus. the adio port of the psd4xx is connected directly to the microcontroller address/data bus (ad0-ad15 for 16 bit bus). the ale input signal latches the address lines internally. in a read bus cycle, data is driven out through the adio port transceivers after the specified access time. the internal adio port connection for a 16 bit multiplexed bus is shown in figure 21. the adio port is in tri-state mode if none of the psd4xx internal devices are selected. 9.2.3 psd4xx interface to non-multiplexed bus figure 22 shows a psd4xx interfacing to a microcontroller with a non-multiplexed address/data bus. the address bus is connected to the adio port, and the data bus is connected to port c and/or port d, depending on the bus width. there is no need for the adio port to latch the address internally, but the user is offered the option to do so in the psd4xx psdsoft software. the data ports are in tri-state mode when the psd4xx is not accessed by the microcontroller. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 39 psd4xx family figure 20. multiplexed bus, 8 or 16-bit data bus micro- controller ad ? [ 7:0 ] ad ? [ 15 : 8 ] a ? [ 15 : 8 ] a ? [ 7:0 ] a ? [ 15 : 8 ] (optional) (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 40 figure 21. adio port, 16-bit multiplexed bus interface ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 adio? adio? adio? adio? adio? adio? adio? adio? adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 r_w ale /as psd4xx internal address bus psd4xx internal data bus latch g latch g psd4xx family the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 41 psd4xx family figure 22. non-multiplexed, 8 or 16-bit data micro- controller d ? [ 15 : 0 ] a ? [ 15 : 0 ] d ? [ 15 : 8 ] d ? [ 7 : 0 ] a [ 23 :16 ] (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx 16-bit data only the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) - obsolet psd4xx family 42 psd4xx family table 7. 8-bit data bus table 8. 16-bit data bus with bhe wrh wrl d15 ?d8 d7 ?d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte table 9. 16-bit data bus with wrh and wrl siz0 a0 d15 ?d8 d7 ?d0 0 0 even byte odd byte 1 0 even byte 1 1 odd byte table 10. 16-bit data bus with siz0, a0 lds uds d15 ?d8 d7 ?d0 0 0 even byte odd byte 1 0 even byte 0 1 odd byte table 11. 16-bit data bus with uds, lds 9.2.4 data byte enable microcontrollers have different data byte orientations with regard to the data bus. the following tables show how the psd4xx handles the byte enable under different bus configurations. even byte refers to locations with address a0 equal to ?? and odd byte as locations with a0 equal to ?? bhe a0 d15 ?d8 d7 ?d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte bhe a0 d7 ?d0 x 0 even byte x 1 odd byte the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) 9.2.5 optional features the psd4xx provides two optional features to add flexibility to the bus interface: 1. address in port a can be configured as high order address (a16-a23) inputs to the zpld for eprom or other decoding. inputs are latched by ale/as if multiplexed bus is selected. other ports can be configured as address input ports for the zpld. these inputs should not be used for eprom decoding and are not latched internally. 2. address out for multiplexed bus only. latched address lines a0-a15 are available on port a, b, c or d. details on the optional features are described in the i/o port section. 9.2.6 bus interface examples the next four figures show the psd4xx interfacing with some popular microcontrollers. the examples show only the basic bus connections; some of the pin names on the psd4xx parts change to reflect the actual pin functions. figure 23 shows the interface to the 80c31. the 80c31 has a 16 bit address bus and an 8-bit data bus. the lower address byte is multiplexed with the data bus. the rd and wr signals are used for accessing the data memory (sram) and the psen signal is for reading program memory (eprom). the ale signal is active high and is used to latch the address internally. port c provides latched address outputs a[7:0]. ports a, b, d, and e (pe2-pe7) can be configured to perform other functions. the rstout reset to the 80c31 is generated by the zpld from the reset input. this configuration eliminates any reset race condition between the 80c31 and the psd4xx. figure 24 shows the 68hc11 interface, which is similar to the 80c31 except the psd4xx generates internal rd and wr from the 68hc11 s e and r/w signals. in figure 25, the intel 80c196 microcontroller is interfaced to the psd4xx. the 80c196 has a multiplexed 16-bit address and data bus. the bhe signal is used for data byte selection. ports c and d are used as output ports for latched address a[15:0]. pins pe6 and pe7 can be programmed as zpld outputs to provide the ready and buswidth control signals to the 80c196. figure 26 shows motorola s mc68331 interfacing to the psd4xx. the mc68331 has a 16-bit data bus and a 24-bit address bus. d15 ?d8 from the mc68331 are connected to port d, and d7 ?d0 are connected to port c. psd4xx family 43 psd4xx family the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 44 psd4xx family figure 23. interfacing psd4xx with 80c31 ea/vp x1 x2 reset int0 int1 t0 t1 p1 . 0 p1 . 1 p1 . 2 p1 . 3 p1 . 4 p1 . 5 p1 . 6 p1 . 7 ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / psen pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 31 19 18 9 12 13 14 15 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 80c31 ad [ 7:0 ] ad [ 7:0 ] reset rstout clock reset clock psd4xx rd wr psen ale 1 2 3 4 5 6 7 8 obsolete product(s) - obsolete product(s) psd4xx family 45 psd4xx family figure 24. interfacing psd4xx with 68hc11 xt ex reset irq xirq modb pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 e r/w reset csi clkin pe0 pe1 / ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r/w pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 8 7 17 19 18 2 34 33 32 43 44 45 46 47 48 49 50 52 51 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 68hc11 psd4xx ad [ 7 : 0 ] ad [ 7 : 0 ] clock reset e ale r/w clock ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 reset obsolete product(s) - obsolete product(s) psd4xx family 46 psd4xx family figure 25. interfacing psd4xx with 80c196 x1 nmi ready cde buswidth reset ach0 / p0 . 0 ach1 / p0 . 1 ach2 / p0 . 2 ach3 / p0 . 3 ach4 / p0 . 4 ach5 / p0 . 5 pcs6 / p0 . 6 pcs7/ p0 . 7 p2 . 0 / txd p2 . 1 / rxd p2 . 2 / exint p2 . 3 / t2clk p2 . 4 / t2rst p2 . 5 / pwm p2 . 6 / t2up ?dn p2 . 7/ t2cap hsi .0 hsi .1 hsi .2 / hso .4 hsi .3 / hso .5 vref angnd ea ad0 /a0 ad1 /a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11 /a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / bhe pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby x2 p3 . 0 /ad0 p3 . 1 /ad1 p3 . 2 /ad2 p3 . 3 /ad3 p3 . 4 /ad4 p3 . 5 /ad5 p3 . 6 /ad6 p3 . 7/ad7 p4 . 0 /ad8 p4 . 1 /ad9 p4 . 2 /ad10 p4 . 3 /ad11 p4 . 4 /ad12 p4 . 5 /ad13 p4 . 6 /ad14 p4 . 7/ad15 rd wr bhe ale inst clkout p1 .0 p1 .1 p1 .2 p1 .3 p1 .4 p1 .5 p1 .6 p1 .7 hso .0 hso .1 hso .2 hso .3 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 11 3 43 14 64 16 6 5 7 4 11 10 8 9 18 17 15 44 42 39 33 38 24 25 26 27 13 12 2 12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 61 40 41 62 63 65 59 58 57 56 55 48 47 46 50 49 44 43 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] reset ready buswidth rd wr bhe ale clkout psd4xx 80c196 obsolete product(s) - obsolete product(s) psd4xx family 47 psd4xx family figure 26. interfacing psd4xx with motorola 68331 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset dsack0 dsack1 irq1 irq2 irq3 irq4 irq5 irq6 irq7 ad0 / a0 ad1 / a1 ad2 / a2 ad3 / a3 ad4 / a4 ad5 / a5 ad6 / a6 ad7 / a7 ad8 / a8 ad9 / a9 ad10 / a10 ad11 / a11 ad12 / a12 ad13 / a13 ad14 / a14 ad15 / a15 ds r / w reset csi clkin pe0 / siz0 pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 cs6 a20 cs7 a21 cs8 a22 cs9 a23 cs10 as r w ds siz0 siz1 clkout csboot br cs0 bg cs1 bgack cs2 fc0 cs3 fc1 cs4 fc2 cs5 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 82 79 85 81 80 66 112 113 114 115 118 119 120 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 ale rw ds siz0 clkout d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] a [ 18 : 0 ] a [ 18 : 0 ] reset psd4xx mc68331 obsolete product(s) - obsolete product(s) psd4xx family 48 psd4xx family 9.3 i/o ports there are 5 programmable 8-bit i/o ports: port a, port b, port c, port d and port e. these ports all have multiple operating modes, depending on the configuration. some of the basic functions are providing input/output for the zpld, or can be used for standard i/o. each port pin is individually configurable, thus enabling a single 8-bit port to perform multiple functions. the i/o ports occupy 256 bytes of memory space as defined by ?siop? refer to the system configuration section for i/o register address offset. to set up the port configuration the user is required to: 1. define i/o port chip select (csiop) in the abel file. 2. initialize certain port configuration registers in the user s program and/or 3. specify the configuration in the psd4xx psdsoft software. 4. unused input pins should be tied to v cc or gnd. the following is a description of the operating modes of the i/o ports. the functions of the port registers are described in later sections. 9.3.1 standard mcu i/o the standard mcu i/o mode provides additional i/o capability to the microcontroller. in this mode, the ports can perform standard i/o functions such as sensing or controlling various external i/o devices. operation options of this mode are as follows: o configuration 1. declare pins or signals which are used as i/o in the abel file. 2. set the bit or bits in the control register to "1". 3. as output port write output data to data out register set direction register to output mode 4. as input port set direction register to input mode read input from data in register the port remains an output or input port as long as the direction register is not changed. 9.3.2 pld i/o the pld i/o mode enables the port to be configured as an input to the zpld, or as an output from the gpld macrocell. the output can be tri-stated with a control signal defined by a product term from the zpld. this mode is configured by the user in the psd4xx psdsoft software, and is enabled upon power up. for a detailed description, see the section on the zpld. o configuration 1. declare pins or signals in the abel file (psdsoft). 2. write logic equations in the abel file. 3. psd compiler maps the pld functions to the psd. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 49 psd4xx family 9.3.3 address out for microcontrollers with a multiplexed address/data bus, the i/o ports in address-out mode are able to provide latched address outputs (a0 ?a15) to external devices. this mode of operation requires the user to: o configuration 1. declare the pins used as address line outputs in the abel file (psdsoft). 2. write ??to the corresponding bit in the control register associated with each i/o port. 3. set the direction register to output mode. 9.3.4 address in there are two address in modes: 1. for port a - as other address line (a2-a7 and a16-a23) inputs to the dpld. additional address inputs included in the eprom decoding must come from port a. the address inputs are latched internally by ale/as if multiplexed bus is specified in psdsoft. 2. for ports c and d ? as address inputs to the zpld for general decoding, should not be used in eprom decoding. o configuration 1. declare pins or signals used as address in in the abel file (psdsoft). 2. write latch equations in the .abl file, e.g., a16.le = ale. 3. include latched address in logic equations. 9.3.5 data port in this mode, the port is acting as a data bus port for a microcontroller which has a non-multiplexed address/data bus. the data port is connected to the data bus of the microcontroller and the adio port is connected to the address bus. o configuration select the non-multiplexed bus option in psd configuration (psdsoft). 9.3.6 alternate function in this mode is per-pin configurable and enables the user to define pin pe7 of port e as automatic power down (apd) clk input. o configuration 1. select input functions in psd configuration. 2. psd compiler assigns pins for the selected options. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 50 psd4xx family port mode port a port b port c port d port e standard mcu i/o yes yes yes yes yes pld i/o yes yes input only * input only * yes * address out yes yes yes yes yes address in yes yes ** yes ** yes ** data port yes yes alternate function in yes peripheral i/o yes open drain yes yes * psd4xxa2 and zpsd4xxa2 only. ** for external decoding. cannot be latched by ale 9.3.7 peripheral i/o this mode enables the microcontroller to read or write to a peripheral though port a. when there is no read/write operation, port a is tri-stated. one of the applications of peripheral i/o is in a dma based design. o configuration 1. declare the pins used as pheripheral i/o in the abel file. 2. write logic equations for psel0 and psel1. 3. write a ??to the pio bit in the vm register to activate the peripheral i/o operation. see the section on peripheral i/o for a detailed description. 9.3.8 open drain outputs this mode enables the user to configure ports c and d pins as open drain outputs. cmos output is the default configuration. writing ??to the corresponding bit in the open drain register changes the pin to open drain output. table 12. operating modes of the i/o ports table 12 summarizes the operating modes of the i/o ports. not all the functions are available to every port. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 51 psd4xx family register name port write/read control register a,b,c,d,e write/read direction register a,b,c,d,e write/read open drain register c,d write/read pld ?i/o register a,b,e read table 13. port configuration registers (pcr) register name port read/write data in register a,b,c,d,e read data out register a,b,c,d,e write/read macrocell out register a,b,e read table 14. port data registers (pdr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pa7 pin pa6 pin pa5 pin pa4 pin pa3 pin pa2 pin pa1 pin pa0 pin table 15. data in register ?port a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pa7 pin pa6 pin pa5 pin pa4 pin pa3 pin pa2 pin pa1 pin pa0 pin = 0 = 0 = 0 = 0 = 0 = 1 = 1 = 1 direction register ?port a ( example: pins pa0 ?pa2 as output, pa3 ?pa7 as input) 9.3.9 port registers there are two sets of registers per i/o port: the port configuration registers (pcr) which consist of four 8-bit registers; and the port data registers (pdr) which include three 8-bit registers. the pcr is used for setting up the port configuration, while the pdr enables the microcontroller to write or read port data or status bits. tables 13 and 14 show the names and the registers and the ports to which they belong. all the registers in the pcr and pdr are 8-bits wide and each bit is associated with a pin in the i/o port. in table 15, the lsb of the data in register of port a is connected to pin pa0, and the msb is connected to pa7. this pin configuration also applies to other registers and ports. for example, in the direction register of port a, writing a hex value of 07 to the register configures pins pa0 ?pa2 as output pins, while pa3 ?pa7 remain as input pins. registers can be accessed by the microcontroller during normal read/write bus cycles. the i/o address offset of the registers are listed in the system configuration section. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 52 9.3.9.1 control register this register is used in both standard mcu i/o mode and address out modes. for setting a standard mcu i/o mode, a ??must be written to the corresponding bit in the register. writing a ??to the register is required for the address out mode. the register has a default value of ??after reset. 9.3.9.2 direction register this register is used to control the direction of data flow in the i/o ports. writing a ??to the corresponding bit in the register configures the port to be an output port, and a ??forces the port to be an input port. the i/o configuration of the port pins can be determined by reading the direction register. after reset, the pins are in input mode. 9.3.9.3 open drain this register determines whether the output pin driver of ports c or d is a cmos driver or an open drain driver. writing a ??to the register selects a cmos driver, while a ??selects an open drain driver. 9.3.9.4 pld ?i/o register this is a read only status register. reading a "1" indicates the corresponding pin is configured as a pld pin. a "0" indicates the pin is an i/o pin. 9.3.9.5 data in register this register is used in the standard mcu i/o mode configuration to read the input pins. 9.3.9.6 data out register this register holds the output data in the standard mcu i/o mode. the contents of the register can also be read. 9.3.9.7 macrocell out register this register enables the user to read the outputs of the gpld macrocell (pa, pb, and pe macrocells). 9.3.9.8 i/o register address offset the i/o register can be accessed by the microcontroller during normal read/write bus cycles. the address of a register is defined as: csiop + register address offset the csiop is the base address that is defined in the abel file and occupies a 256 byte space. the register address offset lies within this 256 byte space. tables 16 and 16a are the address offset of the registers. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) table 16a. register address offset (for 16-bit motorola microcontrollers in 16-bit mode. use table 16 if 8-bit mode is selected.) psd4xx family 53 address offset register name port a port b port c port d port e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open drain 18 19 pld ?i/o 0a 0b 2a 2c macrocell out 0c 0d (psd4xxa2/ zpsd4xxa2) table 16. register address offset address offset register name port a port b port c port d port e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open drain 19 18 pld ?i/o 0b 0a 2b 2d macrocell out 0d 0c (psd4xxa2/ zpsd4xxa2) the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 54 psd4xx family 9.3.10 port a ? functionality and structure port a is the most flexible of all the i/o ports. it can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o o address out ? latched address lines a[0-7] are assigned to pins pa[0-7]. o address in ? input port for other address lines, inputs can be latched by ale. o peripheral i/o figure 27 shows the structure of a port a pin. if the pin is configured as an output port, the multiplexer selects one of its three inputs as output. if the pin is configured as an input, the input connects to : 1. data in register as input in standard mcu i/o mode or 2. pa macrocell as pld input or 3. pa macrocell through a latch latched by ale, as address in input. 9.3.11 port b ? functionality and structure port b is similar to port a in structure. it can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o o address out ? address lines a[0-7] for 8-bit multiplexed bus or address lines a[8-15] for 16-bit multiplexed bus are assigned to pins pb[0-7]. figure 28 shows the structure of a port b pin. if the pin is configured as an output port, the multiplexer selects one of its three inputs as output. if the pin is configured as input, the input connects to : o data in register as input in standard mcu i/o mode or o pb macrocell as pld input the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 55 psd4xx family figure 27. port a pin structure mux pdr port a pin dq d g q dq control gpld input pcr ale wr ale pa . oe gpld output ale wr internal address / data bus data out address pcr dir. reg. latch a [ 0 ?7 ] the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 56 psd4xx family figure 28. port b pin structure mux pdr port b pin dq d g q dq control gpld input pcr wr ale pb .oe gpld output ale wr data out address pcr dir. reg. a[0 ?7] or a[8 ?15] internal address / data bus the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) 9.3.12 port c and port d ? functionality and structure ports c and d are identical in function and structure and each can be configured to perform one or more of the following operating modes: o standard mcu i/o mode o pld input ? direct input to zpld (psd4xxa2 and zpsd4xxa2 only) o address out ? latched address outputs port c: a[0-7] are assigned to pins pc[0-7] port d: a[0-7] for 8-bit multiplexed bus or a[8-15] for 16-bit multiplexed bus are assigned to pins pd0-7] o data port port c: d[0-7] for 8-bit non-multiplexed bus port d: d[8-15] for 16-bit non-multiplexed bus o open drain ? select cmos or open drain driver figures 29 and 30 show the structure of a port c or d pin. if the pin is configured as output port, the multiplexer selects one of the two inputs as output. if the pin is configured as input, the input connects to : o data in register as input in the standard mcu i/o mode or o zpld input (psd4xxa2 and zpsd4xxa2 only) 9.3.13 port e ? functionality and structure port e can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o (psd4xxa2 and zpsd4xxa2 only) o address out ? latched address lines a[0-7] are assigned to pins pe[0-7] o alternate function in ? in this mode, the inputs to port e pins are: pe0 bhe or psen or wrh or uds or siz0 pe1 ? ale pe7 apd clk :clock input for automatic power down counter figure 31 shows the structure of a port e pin. the control logic block selects one of four sources through the multiplexer for pin output. if the pin is configured as input, the input goes to: o data in register as input in standard mcu i/o mode or o pe macrocell as pld input (psd4xxa2 and zpsd4xxa2 only) or o alternate function in psd4xx family 57 psd4xx family the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 58 psd4xx family figure 29. port c pin structure mux pdr port c pin dq d g q dq control gpld input ** pcr wr ale ale wr data * data out address pcr dir. reg. d [ 0 7 ] a [ 0 7 ] internal address / data bus *data bus d [0 ?] is not connected to gpld?nput. **gpld?nput is available on a2 versions only. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) - obsolet psd4xx family 59 psd4xx family figure 30. port d pin structure mux pdr port d pin dq d g q dq control gpld input ** pcr wr ale ale wr data * data out address pcr dir. reg. d [8 ?5] a [ 0 7 ] or a [8 ?5] internal address / data bus *data bus d [8?5] is not connected to gpld?nput. **gpld?nput is available on a2 versions only. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) - obsolet psd4xx family 60 psd4xx family figure 31. port e pin structure mux pdr port e pin dq d g q dq control gpld input * alt func. in pcr wr ale pe .oe gpld output ale wr data out address pcr dir. reg. internal address / data bus *gpld?nput is available on a2 versions only. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 61 psd4xx family 9.4 memory block the psd4xx provides eprom memory for code storage and sram memory for scratch pad usage. chip selects for the memory blocks come from the dpld decoding logic and are defined by the user in the psdsoft software. figure 32 shows the organization of the memory block. the psd4xx family uses zero-power memory techniques that place memory into standby mode between mcu accesses. the memory becomes active briefly after an address transition, then delivers new data to the outputs, latches the outputs, and returns to standby. this is done automatically and the designer has to do nothing special to benefit from this feature. both the eprom and sram have this feature. 9.4.1 eprom the psd4xx provides three eprom densities: 256kbit, 512kbit, or 1mbit. the eprom is divided into four 8k, 16k or 32k byte blocks. each block has its own chip select signals (es0 ?es3). the eprom can be configured as 32k x 8, 64k x 8 or 128k x 8 for microcontrollers with an 8-bit data bus. for 16-bit data buses, the eprom is configured as 16k x 16, 32k x 16 or 64k x 16. 9.4.2 sram the sram has 16kbits of memory, organized as 2k x 8 or 1k x 16. the sram is enabled by chip select signal rs0 from the dpld. the sram has a battery back-up (stby) mode. this back-up mode is invoked when the v cc voltage drops under the vstdby voltage by approximately 0.7 v. the vstdby voltage is connected only to the sram and cannot be lower than 2.7 volts. 9.4.3 memory select map the eprom and sram chip select equations are defined in the abel file in terms of address and other dpld inputs. the memory space for the eprom chip select (es0 es3) should not be larger than the eprom block (8kb, 16kb, or 32kb) it is selecting. the following rules govern how the internal psd4xx memory selects/space are defined: o the eprom blocks address space cannot overlap o sram, internal i/o and peripheral i/o space cannot overlap o sram, internal i/o and peripheral i/o space can overlap eprom space, with priority given to sram or i/o. the portion of eprom which is overlapped cannot be accessed. the peripheral i/o space refers to memory space occupied by peripherals when port a is configured in the peripheral i/o mode. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 62 9.4.4 memory select map for 8031 application the 8031 family of microcontrollers has separate code memory space and data memory space. this feature requires a different memory select map. two modes of operation are provided for 8031 applications. the selection of the modes is specified in the psd4xx psdsoft software (psdconfiguration): o separate space mode in this mode, the psen signal is used to access code from eprom, and the rd signal is used to access data from sram. the code memory space is separated from the data memory space. o combined space mode in this mode, the eprom can be accessed by psen or rd. the eprom is used for code and data storage. the memory block's address space cannot overlap. if data and code memory blocks must overlap each other, the rd signal can be included as an additional address input in generating the eprom chip select signals (es0 ?es3). in this case the eprom access time is from the rd valid to data valid. figures 32a and 32b show the memory configuration in the two modes. in some applications it is desirable to execute program codes in sram. the psd4xx provides this option by enabling psen to access sram. to activate this option, the srcode bit of the vm register must be set to ??(see table 17). sram space can overlap eprom space and has priority when psen is used. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** ** srcode pio 1 = on 1 = on * = reserved for future use, bits set to zero. table 17. vm register the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 63 figure 32. memory block diagram (128kb eprom) es0 es1 es2 es3 16k x 8 16k x 8 1k x 8 1k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 sram block rs0 odd byte odd byte d [ 8 ?15 ] even byte d [ 0 ?7 ] eprom blocks the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 64 psd4xx family figure 33a. 8031 memory modes eprom dpld sram es0 es1 es2 es3 rs0 rd oe oe srcode en psen separate space mode figure 33b. 8031 memory modes eprom dpld sram es0 es1 es2 es3 rs0 psen rd rd oe oe srcode en psen rd combined space mode the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 65 psd4xx family the psd4xx architecture (cont.) figure 34. port a in peripheral i/o mode rd psel0 psel1 d0 ?d7 wr pa0 ?pa7 9.4.5 peripheral i/o the peripheral i/o mode is one of the operating modes of port a. in this mode, port a is connected to the data bus of peripheral devices. port a is enabled only when the microcontroller is accessing the devices, otherwise the port is tri-stated. this feature enables the microcontroller to access external devices without requiring buffers and decoders. figure 34 shows the structure of port a in the peripheral i/o mode. the memory address space occupied by the devices are defined by two signals: psel0 and psel1. the signals are direct outputs from the decoding pld (dpld). whenever any of the signals is active, the port a driver is enabled, and the direction of the data flow is determined by the rd/wr signals. the peripheral i/o mode and the peripheral select signals are configured and defined in the psdsoft software (see the section on i/o port for configuration). the pio bit in the vm register (see table 17) also needs to be set to ??by the user to initialize the peripheral i/o mode. the peripheral i/o mode can be used, for example, in dma applications where the microcontroller does not support dma operations, such as tri-stating the address/data bus. figure 35 shows a block diagram of a microcontroller and psd4xx based design that makes use of this mode. in this application, the microcontroller has a multiplexed bus which is connected to the adio port. the c and d ports connect to the peripheral address bus and are both configured in address out mode. port a is configured in the peripheral i/o mode and is connected to the peripheral data bus. ports b and e are used to generate control signals. during normal activity, the microcontroller has access to any peripheral (memory or i/o device) through the psd4xx device. when there is a dma request, the microcontroller tri-states the address bus on ports c and d by writing a ??to the port direction registers. the dma controller then takes over the data and address buses after receiving acknowledgement from the microcontroller. obsolete product(s) - obsolete product(s) psd4xx family 66 figure 35. psd4xx peripheral i/o configuration micro- controller ad [ 0 ?7 ] a [ 8 ?5 ] a [ 0 ?7 ] a [ 8 ?15 ] d [ 0 ?7 ] dma ack adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx memory i/o device dma controller peripheral # 1 peripheral # 2 dma req rd wr csi the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 67 psd4xx family 9.5 power management unit the psd4xx provides many power saving options. by configuring the pmmrs (power management mode registers), the user can reduce power consumption. table 18 shows the bit configuration of the pmmr0 and pmmr1. the microcontroller is able to control the power consumption by changing the pmmr bits at run time. 9.5.1 standby mode there are two standby modes in the psd4xx: o power down mode o sleep mode 9.5.1.1 power down mode in this mode, the internal devices are shut down except for the i/o ports and the zpld. there are three ways the psd4xx can enter into the power down mode: by controlling the csi input, by activating the automatic power down (apd) logic and the zpld, or when none of the inputs are changing and the turbo bit is off. o the csi the csi input pin is an active low signal. when low, the signal selects and enables the psd4xx. the psd4xx enters into power down mode immediately when the signal turns high. this signal can be controlled by the microcontrollers, external logic or it can be grounded. the csi input turns off the internal bus buffers in standby mode. the address and control signals from the microcontroller are blocked from entering the zpld as inputs. o the apd logic the apd unit enables the user to enter a power down mode independent of controlling the csi input. this feature eliminates the need for external logic (decoders and latches) to power down the psd. the apd unit concept is based on tracking the activity on the ale pin. if the apd unit is enabled and ale is not active, the 4-bit apd counter starts counting and will overflow after 15 clocks, generating a pd (power down) signal powering down the psd. if sleep mode is enabled, then pd signal will also activate the sleep mode. immediately after ale starts pulsing the psd will get out of the power down or sleep mode. the operation of apd is controlled by the pmmr (see figure 36a). pmmr1 bit 0 selects the source of the apd counter clock. after reset the apd counter clock is connected to pe7 (apd clk) on the psd. in order to guarantee that the apd will not overflow there should be less than 15 apd clocks between two ale pulses. if clkin frequency is adequate, then it can be connected to the apd and pe7 is used for other functions. the next step is to select the ale power down polarity. usually, mcus entering power down will freeze their ale at logic high or low. by programming bit 1 of pmmr0 the power down polarity can be defined for the apd. if the apd detects that the ale is in the power down polarity for 15 apd counter clocks then the psd will enter a power down mode. to enable the apd operation, bit 2 in the pmmr0 should be set high. 9.5.1.2 sleep mode the sleep mode is activated if the sleep en bit, the apd en bit, and the ale polarity bit in the pmmr are set, and the apd counter has overflowed after 15 clocks (see figure 36). in sleep mode the psd4xx consumes less power than the power down mode. in this mode, the zpld still monitors the inputs and responds to them. as soon as the ale starts pulsing, the psd4xx exits the sleep mode. the psd access time from sleep mode is specified by t lvdv1 . the zpld response time to an input transition is specified by t lvdv2 . the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 68 clr clk apd counter apd clk pmmr1 - bit 0 to other circuits mux apd clear logic apd enable pmmr0 - bit 2 ale polarity pmmr0 - bit 1 ale reset apd clk clkin csi sleep enable pmmr1 - bit 1 sleep mode eprom select sram select i/o select power down pd z p l d figure 36. power management unit figure 36a. automatic power down unit (apd) flow chart apd disabled need apd clk yes yes no no reset set apd clk in pmmr1 bit 0 set ale pd polarity in pmmro bit 1 csi = "1" need sleep mode set sleep mode in pmmr1 bit 1 ale idle and 15 apd clock ale idle and 15 apd clock ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 disable clocks zpld aclk, zpld rclk, tmr zpld disable clocks zpld aclk, zpld rclk, tmr zpld psd in power down mode psd in sleep mode the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 69 apd en bit ale power ale status apd counter down polarity 0 x x not counting 1 x pulsing not counting 11 1 counting (activates standby mode after 15 clocks) 10 0 counting (activates standby mode after 15 clocks) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr clk zpld zpld zpld apd ale pd * rclk aclk turbo cmiser enable polarity 1 = off 1 = off 1 = off 1 = off 1 = on 1 = on 1 = high pmmr0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** ** sleep apd clk mode 1 = on 1 = clkin pmmr1 table 18. power management mode registers (pmmr0, pmmr1) table 19. apd counter operation bit 0 * = should be set to high (1) to operate the apd. bit 1 0 = ale power down (pd) polarity low. 1 = ale power down (pd) polarity high. bit 2 0 = automatic power down (apd) disable. 1 = automatic power down (apd) enable. bit 3 0 = eprom/sram cmiser is off. 1 = eprom/sram cmiser is on. bit 4 0 = zpld turbo is on. zpld is always on. 1 = zpld turbo is off. zpld will power down when inputs are not changing. bit 5 0 = zpld clock input into the array from the clkin pin input is connected. every clock change will power up the zpld when turbo bit is off. 1 = zpld clock input into the array from the clkin pin input is disconnected. bit 6 0 = zpld clock input into the the macrocell registers from the clkin pin input is connected. 1 = zpld clock input into the the macrocell registers from the clkin pin input is disconnected. bit 7 * = in the psd4xx should be set to high (1) bit 0 0 = automatic power down unit clock is connected to port e7 (pe7) alternate function input. 1 = automatic power down unit clock is connected to the psd clock input (clkin). bit 1 0 = sleep mode disabled. 1 = sleep mode enabled. bit 2 7 0 = reserved for future use, should be set to zero. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 70 9.5.2 other power saving options the psd4xx provides additional power saving options. these options, except the sram standby mode, can be enabled/disabled by setting up the corresponding bit in the pmmr. o eprom the eprom power consumption in the psd is controlled by bit 3 in the pmmr0 ?eprom cmiser. upon reset the cmiser bit is off. this will cause the eprom to be on at all times as long as csi is enabled (low). the reason this mode is provided is to reduce the access time of the eprom by 10 ns relative to the low power condition when cmiser is on. if csi is disabled (high) the eprom will be deselected and will enter standby mode (off) overriding the state of the cmiser. if cmiser is set (on) then the eprom will enter the standby mode when not selected. this condition can take place when csi is high or when csi is low and the eprom is not accessed. for example, if the mcu is accessing the sram, the eprom will be deselected and will be in low power mode. an additional advantage of the cmiser is achieved when the psd is configured in the by 8 mode (8 bit data bus). in this case an additional power savings is achieved in the eprom (and also in the sram) by turning off 1/2 of the array even when the eprom is accessed (the array is divided internally into odd and even arrays). the power consumption for the different eprom modes is given in the dc characteristics table under i cc (dc) eprom adder. o sram standby mode the sram has a dedicated supply voltage v stby that can be used to connect a battery. when v cc becomes lower than v stby 0.6 then the psd will automatically connect the v stby as a power source to the sram. the sram standby current (i stby ) is typically 0.5 ?. sram data retention voltage v df is 2 v minimum. o zero power zpld zpld power/speed is controlled by the zpld_turbo bit (bit 4) in the pmmr0. after reset the zpld is in turbo mode and runs at full power and speed. by setting the bit to ?? the turbo mode is disabled and the zpld is consuming zero power current if the inputs are not switching for an extended time of 70 ns. the propagation delay time will be increased by 10ns after the turbo bit is set to ??(turned off) if the inputs change at a frequency of less than 15 mhz. the psd4xx architecture (cont.) obsolete product(s) - obsolete product(s) psd4xx family 71 psd4xx family the psd4xx architecture (cont.) port configuration pin status i/o port unchanged zpld output depend on inputs to the zpld address out undefined data port tri-stated peripheral i/o tri-stated table 20. i/o pin status during power down and sleep mode o input clock the psd4xx provides the option to turn off the clock inputs to save ac power consumption. the clock input (clkin) is used as a source for driving the following modules: o zpld array clock input o zpld macrocell clock flip flop o apd counter clock during power down or if any of the modules are not being used the clock to these modules should be disabled. to reduce ac power consumption, it is especially important to disable the clock input to the zpld array if it is not used as part of a logic equation. the zpld array clock can be disabled by setting pmmr0 bit 5 (zpld aclk). the zpld macrocell clock input can be disabled by setting pmmr0 bit 6 (zpld rclk). the timer clock can be disabled by setting pmmr0 bit 7 (tmr clk). the apd counter clock will be disabled automatically if power down or sleep mode is entered through the apd unit. the input buffer of the clkin input will be disabled if bits 5 ?7 pmmr0 are set and the apd has overflowed. pld pld access access propagation recovery time recovery delay time to time to normal normal operation access power down normal t pd 0 no access t lvdv (note 1) sleep t lvdv2 t lvdv3 no access t lvdv1 (note 2) (note 3) summary of psd4xx timing and standby current during power down and sleep modes notes: 1. power down does not affect the operation of the zpld. the zpld operation in this mode is based only on the zpld_turbo bit. 2. in sleep mode any input to the zpld will have a propagation delay of t lvdv2 . 3. pld recovery time to normal operation after exiting sleep mode. an input to the zpld during the transition will have a propagation delay time of t lvdv3 . obsolete product(s) - obsolete product(s) psd4xx family 72 psd4xx family 10.0 page register the psd4xx has a programmable security bit which offers protection from unauthorized duplication. when the security bit is set, the contents of the eprom, the psd4xx non-volatile configuration bits and zpld data cannot be read by eprom programmers. the security bit is set through the psdsoft software and is embedded in the compiled output file. the security bit is uv erasable and a secured part can be erased and then re-programmed. 11.0 security protection figure 35. page register dpld rs0 gpld zpld es0 ?3 pgr0 pgr1 pgr2 pgr3 r/w d0 d0 ?d3 d1 d2 d3 q0 q1 q2 q3 page reg. reset the page register is 4 bits wide and consists of four d flip flops.the outputs of the register (pgr0 ?pgr3) are connected to the input bus of the zpld. by including the four outputs as inputs to the dpld, the addressing capability of the microcontroller is increased by a factor of 16. figure 37 shows the page register block diagram. inputs to the four flip flops are connected to data bus d0-d3. the output of the register can be read by the microcontroller. the register can operate as an independent register to the microcontroller if page mode is not implemented. obsolete product(s) - obsolete product(s) psd4xx family 73 12.0 system configuration table 21. register address offset table 21a. register address offset (for 16-bit motorola microcontrollers in 16-bit mode. use table 21 if 8-bit mode is selected.) register address register address name offset name offset page register e1 vm c1 pmmr1 b0 pmmr0 b1 the csiop signal, which is generated by the dpld, selects the internal i/o devices or registers. the csiop signal takes up 256 bytes of address space and is defined by the user in the psdsoft software. the following is an address offset map for the various devices relative to the csiop base address. some motorola 16-bit microcontrollers have a different data bus/data byte orientation. this requires a different address offset for the internal psd4xx i/o devices or registers. tables 21a and 22a in this section are for this group of microcontrollers which include the m68hc16, m68302 and m683xx. register address register address name offset name offset page register e0 vm c0 pmmr1 b1 pmmr0 b0 obsolete product(s) - obsolete product(s) psd4xx family 74 the following table is the address map offset of the i/o port registers. table 22a. register address offset (for 16-bit motorola microcontrollers in 16-bit mode. use table 22 if 8-bit mode is selected.) address offset register name port a port b port c port d port e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open drain 18 19 pld ?i/o 0a 0b 2a 2c macrocell out 0c 0d (psd4xxa2/ zpsd4xxa2) table 22. i/o register address offset address offset register name port a port b port c port d port e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open drain 19 18 pld ?i/o 0b 0a 2b 2d macrocell out 0d 0c (psd4xxa2/ zpsd4xxa2) 12.0 system configuration (cont.) obsolete product(s) - obsolete product(s) psd4xx family 75 psd4xx family system configuration (cont.) register name register function data in this register is used to read the inputs on the port pins. control a 0 ? sets the corresponding port pin in address out mode. a 1 ? sets the pin in mcu i/o mode. data out holds the output data in the mcu i/o mode. this register is used to control the data flow in the i/o ports. direction a 0 ? sets the corresponding pin as an input pin. a 1 ? sets the pin as an output pin. open drain a 0 ? sets the corresponding pin driver as a cmos driver. a 1 ? sets the pin driver as an open drain driver. pld ?i/o a read only status register; a 1 ? indicates the corresponding pin is configured as a pld pin. macrocell out this register holds the outputs of the gpld macrocells. page register a 4-bit register that supports paging. 1. configures the psd4xx sram to be accessed by psen ? as vm program space (8031 design). 2. enables the peripheral i/o mode of port a. pmmr0 power management registers; enables the psd4xx power down pmmr1 mode and other power saving configurations. table 23. register function obsolete product(s) - obsolete product(s) port configuration reset stand-by mode port i/o input unchanged zpld output active depend on inputs to the zpld address out tri-stated not defined data port tri-stated tri-stated peripheral i/o tri-stated tri-stated psd4xx family 76 psd4xx family register name device reset state control port a, b, c, d, e set to ? (address out mode) data out (data or address) port a, b, c, d, e set to ?? direction port a, b, c, d, e set to ???input mode open drain port c, d set to ???cmos outputs page register page logic set to ? pmmr0, pmmr1 power management unit set to ? vm volatile memory set to ? system configuration (cont.) table 24. registers reset values table 25. i/o pin status during reset and standby mode 12.1 reset input the reset input to the psd4xx (reset) is an active low signal which resets some of the internal devices and configuration registers. the timing diagram in the ac/dc characterization section shows the reset signal timing requirement. the active low range has a minimum t1 duration. after the rising edge of reset, the psd4xx remains in reset during t2 range. (see figure 48). the psd4xx must be reset at power up before it can be used. 12.2 zpld and memory during reset while the reset input is active, the zpld generates outputs as defined in the psdabel equations. the eprom and sram blocks respond to the microcontroller bus cycle during reset, but the data is not guaranteed. 12.3 register values during and after reset table 24 summarizes the status of the volatile register values during and after reset. the default values of the volatile registers are ??after reset. 12.4 zpld macrocell initialization the d flip flops in the macrocells in the gpld can be cleared by: o a product term (.re) defined by the user in psdabel, or o the macro-rst (reset) input, enabled and defined in psdabel. obsolete product(s) - obsolete product(s) psd4xx family 77 psd4xx family symbol parameter condition min max unit t stg storage temperature cldcc ?65 + 150 ? pldcc ?65 + 125 ? commercial 0 + 70 ? operating temperature industrial ?40 + 85 ? voltage on any pin with respect to gnd ?0.6 + 7 v v pp programming supply voltage with respect to gnd ?0.6 + 14 v v cc supply voltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v 13.0 specifications note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. type temperature v cc v cc tolerance speed grades available -70 -90 -15 -20 -25 commercial 0 c to +70? + 5 v 10% x x + 3 v 10% x x industrial 40 c to +85? + 5 v 10% x + 3 v 10% x symbol parameter condition min typ max unit v cc supply voltage all speeds 4.5 5.0 5.5 v v cc supply voltage zpsd4xxv versions 2.7 3.0 5.5 v only, all speeds 13.2 operating range 13.3 recommended operating conditions 13.1 absolute maximum ratings obsolete product(s) - obsolete product(s) psd4xx family 78 psd4xx family specifications (cont.) 13.4 ac/dc parameters the following tables describe the ad/dc parameters of the psd4xx family: o dc electrical specification o ac timing specification zpld timing combinatorial delays synchronous clock mode asynchronous clock mode microcontroller timing read timing write timing peripheral mode timing power down and reset timing following are some issues concerning the parameters presented: o in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd4xx is in each mode. also the supply power is considerably different if the zpld_turbo bit is "off" and eprom_cmiser is "on". o the ac power component gives the zpld, eprom, and sram ma/mhz specification. figure 38 shows the zpld ma/mhz as a function of the number of product terms (pt) used. o in the zpld timing parameters add the required delay when zpld_turbo is "off". o in the mcu timing specification add the required time delay when eprom_cmiser is "on". figure 38a. typical i cc /frequency consumption (psd4xxa1 and zpsd4xxa1 versions) 0 10 20 60 50 80 70 90 100 40 30 01015 5 20 25 pt100% pt25% composite frequency at pld inputs (mhz) i cc ?(ma) 10 turbo on turbo on turbo off turbo off v cc = 5 v obsolete product(s) - obsolete product(s) psd4xx family 79 figure 38b. typical i cc /frequency consumption (psd4xxa2 and zpsd4xxa2 versions) 0 20 60 80 100 120 40 01015 5 20 25 pt100% pt25% composite frequency at pld inputs (mhz) i cc ?(ma) turbo on turbo on turbo off turbo off figure 38c. typical i cc /frequency consumption (psd4xxa1v and zpsd4xxa2v versions) 0 10 20 30 40 50 01015 5 20 25 pt100% pt25% composite frequency at pld inputs (mhz) i cc ?(ma) turbo on turbo on turbo off turbo off specifications (cont.) v cc = 5 v v cc = 3 v obsolete product(s) - obsolete product(s) psd4xx family 80 conditions composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % eprom access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % sleep = 90% number of product terms used (from fitter report) = 29 pt % of total product terms = 29/118 = 24.6% turbo = off cmiser = on 8-bit bus mode calculation (typical numbers used) i cc total = isleep x %sleep + %normal x ( i cc (ac) + i cc (dc) ) = isleep x %sleep + %normal x (%eprom x 0.8 ma/mhz x freq ale + %sram x 1.4 ma/mhz x freq ale + %pld x 2.5 ma/mhz x freq pld + #pt x 400 ?/pt) = 10 ? x 0.90 + 0.1 x (0.8 x 0.8 ma/mhz x 4 mhz + 0.15 x 1.4 ma/mhz x 4 mhz + 0.95 x 2.5 x 8 + 29 x 0.4 ma/pt) = 0.9 ? + 0.1 x (2.56 + 0.84 + 19 + 11.6 ma) = 0.9 ? + 0.1 x 34 = 0.9 ? + 3.4 ma = 3.4 ma notes: standby current consumption is handled similarly to sleep mode shown above. calculation assumes i out = 0 ma. 13.5 example of zpsd4xx typical power calculation at v cc = 5.0 v specifications (cont.) obsolete product(s) - obsolete product(s) psd4xx family 81 symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high level input voltage 4.5 v < v cc < 5.5 v 2 v cc + 0.5 v v il low level input voltage 4.5 v < v cc < 5.5 v 0.5 0.8 v v ih1 reset high level input voltage (note 1) 0.8 v cc v cc + 0.5 v v il1 reset low level input voltage (note 1) ?.5 0.2 v cc ?.1 v v hys reset pin hysteresis 0.3 v v ol output low voltage i ol = 20 ?, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.15 0.45 v v oh output high voltage i oh = 20 ?, v cc = 4.5 v 4.4 4.49 v i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v sby sram standby voltage 2.7 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stdby pin) v cc > v sby 0.1 0.1 ? v df sram data retention voltage only on v stby 2v i sb1 standby supply power down mode csi >v cc ?.3 v (note 2) 50 100 ? (psd4xx) current sleep mode csi >v cc ?.3 v (note 3) 30 40 ? i sb2 standby supply power down mode csi >v cc ?.3 v (note 2) 25 50 ? (zpsd4xx) current sleep mode csi >v cc ?.3 v (note 3) 10 20 ? i li input leakage current v ss < v in < v cc ? ?.1 1 a i lo output leakage current 0.45 < v in < v cc ?0 5 10 ? zpld_turbo = off, see i sb1 f = 0 mhz (note 4) and i sb2 i cc (dc) operating zpld adder zpld_turbo = on, (note 4a) supply current f = 0 mhz 400 700 ?/pt eprom adder f = 0 mhz 0 ma sram adder f = 0 mhz 0 ma zpld ac adder see fig. 38 4 ma/mhz cmiser = on and eprom ac adder (8-bit bus mode) 0.8 2 ma/mhz all other cases 1.8 4 ma/mhz i cc (ac) cmiser = on and (note 4a) (8-bit bus mode) 1.4 2.7 ma/mhz sram ac adder cmiser = on and 2 4 ma/mhz (16-bit bus mode) cmiser = off 3.8 7.5 ma/mhz 13.6 dc characteristics (5 v 10% versions) notes: 1. reset input has hysteresis. v il1 is valid at or below 0.2v cc ?.1. v ih1 is valid at or above 0.8v cc . 2. csi is high or internal power down mode is active. 3. sleep mode bit is set and internal power down is active. 4. see zpld i cc /frequency power consumption graph for details. 4a. i out = 0 ma. obsolete product(s) - obsolete product(s) psd4xx family 82 -70 -90** -15 zpld_turbo symbol parameter conditions min max min max min max off * unit i/o input or feedback to t pd combinatorial output port b, e 25 30 34 add 10 ns t rpd registered input to (note 1) 27 32 36 add 10 ns combinatorial output t ea input to output enable any input 25 28 32 add 10 ns t er input to output disable any input 25 28 32 add 10 ns t arp register clear or preset any input 27 30 34 add 10 ns delay t arpw register clear or preset any input 20 25 29 ns pulse width t ard array delay 16 18 22 ns combinatorial delays (5 v 10% versions) note: 1. port a and latched address from adio (a0, a1, a8 ?a15). * * if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameters. ** the -90 speed is available only on industrial temperature range product. 13.7 ac/dc parameters ? zpld timing parameters (5 v 10% versions) -70 -90** -15 zpld_turbo symbol parameter conditions min max min max min max off * unit maximum frequency external feedback 1/(t s + t co ) 30.30 27.03 23.81 mhz maximum frequency f max internal feedback (f cnt ) 1/(t s +t co ?0) 43.48 37.04 31.25 mhz maximum frequency pipelined data 1/(t ch + t cl ) 50.00 41.67 33.33 mhz t s input setup time any input 15 17 20 add 10 ns t h input hold time any input 0 0 0 0 ns t ch clock high time clock input 10 12 15 0 ns t cl clock low time clock input 10 12 15 0 ns t co clock to output delay clock input 18 20 22 0 ns t ard array delay for product term expansion any macrocell 16 18 22 0 ns t min minimum clock period t ch + t cl 20 24 29 0 ns synchronous clock mode (5 v 10%) * * if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameters. ** the -90 speed is available only on industrial temperature range product. obsolete product(s) - obsolete product(s) psd4xx family 83 -70 -90** -15 zpld_turbo symbol parameter conditions min max min max min max off * unit maximum frequency external feedback 1/(t sa + t coa ) 26.32 25.00 20.41 mhz maximum frequency f maxa internal feedback 1/(t sa +t co a ?0) 35.71 33.33 25.64 mhz (f cnta ) (note 1) maximum frequency pipelined data 1/(t ch + t cl ) 41.67 41.67 33.33 mhz t sa input setup time any input 8 8 12 add 10 ns t ha input hold time any input 8 8 12 0 ns t cha clock high time any input 12 12 15 0 ns t cla clock low time any input 12 12 15 0 ns t coa clock to output any input 30 32 37 add 10 ns delay to port b t ard array delay for product term any macrocell 16 18 22 0 ns expansion t mina minimum clock period 1/f cnt 28 30 43 0 ns asynchronous clock mode (5 v 10% , note 1) ac/dc parameters ? zpld timing parameters (5 v 10% versions) note: 1. only port b has asynchronous outputs. clock into macrocell flip flop is generated by a product term. * * if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameters. ** the -90 speed is available only on industrial temperature range product. obsolete product(s) - obsolete product(s) psd4xx family 84 explanation of ac symbols for non zpld timing. example: t avlx time from address valid to ale invalid. a address l logic level low or ale t r/w c power down n reset t time d input data p port signal v valid e ? q output data x no longer a valid logic level h logic level high r wr, uds, lds, ds, iord, psen z float i interrupt s chip select -70 -90* -15 eprom_cmiser symbol parameter conditions min max min max min max on unit t lvlx ale or as pulse width 18 20 28 0 ns t avlx address setup time (note 3) 5 6 10 0 ns t lxax address hold time (note 3) 7 8 11 0 ns t avqv address valid to data valid (note 3) 70 90 150 add 10 ns t slqv cs valid to data valid 80 100 150 add 10 ns rd to data valid 8/16-bit bus (note 1) 20 32 40 0 ns t rlqv rd to data valid 8-bit bus, 8031 separate (note 2) 32 38 45 0 ns mode t rhqx rd data hold time (note 1) 0 0 0 0 ns t rlrh rd pulse width (note 1) 30 32 38 0 ns t rhqz rd to data high-z (note 1) 22 25 33 0 ns t ehel e pulse width 30 32 38 0 ns t theh r/w setup time to enable 81018 0 ns t eltl r/w hold time after enable 000 0ns in 16-bit data bus 20 30 38 0 ns t avpv address input valid to mode (note 9) address output delay in 8-bit data bus 22 32 48 0 ns mode (note 9) read timing (5 v 10% versions) notes: 1. rd timing has the same timing as psen, ds, lds, uds signals. 2. rd and psen have the same timing for 8031 mode. 3. any input used to select an internal psd4xx function. 4. in multiplexed mode latched address generated from adio delay to address output on any port. * the -90 speed is available only on industrial temperature range product. 13.8 microcontroller interface ? ac/dc parameters (5 v 10% versions) obsolete product(s) - obsolete product(s) psd4xx family 85 -70 -90* -15 eprom_cmiser symbol parameter conditions min max min max min max on unit t lvlx ale or as pulse width 18 20 28 ns t avlx address setup time (note 1) 5 6 10 ns t lxax address hold time (note 1) 7 8 11 ns t avwl address valid to leading edge of wr (notes 1 and 3) 18 20 30 ns t slwl cs valid to leading edge of wr (note 3) 22 25 35 ns t dvwh wr data setup time (note 3) 12 15 22 ns t whdx wr data hold time (note 3) 5 5 5 ns t wlwh wr pulse width (note 3) 18 20 28 ns t whax trailing edge of wr to address invalid (note 3) 0 0 0 ns t whpv trailing edge of wr to port output valid (note 3) 25 30 38 ns in 16-bit data bus 20 30 38 ns address input valid to mode (note 2) t avpv address output delay in 8-bit data bus 22 32 48 ns mode (note 2) write timing (5 v 10%) microcontroller interface ? ac/dc parameters (5 v 10% versions) notes: 1. any input used to select an internal psd4xx function. 2. in multiplexed mode latched address generated from adio delay to address output on any port. 3. wr timing has the same timing as e, ds, lds, uds, wrl, wrh signals. * the -90 speed is available only on industrial temperature range product. obsolete product(s) - obsolete product(s) psd4xx family 86 -70 -90** -15 zpld_turbo symbol parameter conditions min max min max min max off * unit t avqv (pa) address valid to data valid (note 3) 45 55 62 add 10 ns t slqv (pa) cs valid to data valid 55 55 62 add 10 ns rd to data valid (notes 1 and 4) 22 26 45 0 ns t rlqv (pa) rd to data valid 8031 mode 32 38 45 0 ns t dvqv (pa) data in to data out valid 22 22 26 0 ns t qxrh (pa) rd data hold time (note 1) 0 0 0 0 ns t rlrh (pa) rd pulse width (note 1) 25 30 38 0 ns t rhqz (pa) rd to data high-z (note 1) 20 25 33 0 ns port a peripheral data mode read timing (5 v 10%) -70 -90** -15 zpld_turbo symbol parameter conditions min max min max min max off unit t wlqv (pa) wr to data propagation delay (note 2) 25 27 35 0 ns t dvqv (pa) data to port a data propagation delay (note 5) 22 22 26 0 ns t whqz (pa) wr invalid to port a tri-state (note 2) 20 25 33 ns port a peripheral data mode write timing (5 v 10%) notes: 1. rd timing has the same timing as psen, ds, lds, uds signals. 2. wr timing has the same timing as e, ds, lds, uds, wrl, wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. * * if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameters. ** the -90 speed is available only on industrial temperature range product. microcontroller interface ? ac/dc parameters (5 v 10% versions) obsolete product(s) - obsolete product(s) psd4xx family 87 microcontroller interface ? ac/dc parameters (5 v 10% versions) -70 -90* -15 zpld_turbo symbol parameter conditions min max min max min max off unit t lvdv ale access time from power down 100 120 150 add 10 ns t lvdv1 ale or csi access time from sleep 120 150 200 0 ns t lvdv2 zpld propagation delay in sleep mode 600 600 600 0 ns t lvdv3 zpld recovery time after sleep mode 250 250 250 0 ns t chcl apd clock high time using pe7 10 12 15 0 ns t clch apd clock low time using pe7 10 12 15 0 ns f max apd maximum frequency using pe7 35.00 30.00 22.00 0 mhz t 1 reset active low time 150 200 300 0 ns t 2 reset high to operational device 150 200 300 0 ns power down and reset timing (5 v 10%) * the -90 speed is available only on industrial temperature range product. obsolete product(s) - obsolete product(s) psd4xx family 88 symbol parameter conditions min typ max unit v cc supply voltage all speeds 2.7 3 5.5 v v ih high level input voltage 2.7 v < v cc < 5.5 v .7 v cc v cc +.5 v v il low level input voltage 2.7 v < v cc < 5.5 v 0.5 .3 v cc v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v ol output low voltage i ol = 20 ?, v cc = 2.7 v 0.01 0.1 v i ol = 4 ma, v cc = 2.7 v 0.15 0.45 v v oh output high voltage i oh = 20 ?, v cc = 2.7 v 2.9 2.99 v i oh = 1 ma, v cc = 2.7 v 2.4 2.6 v v sby sram standby voltage 2.7 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 ? v df sram data retention voltage only on v stby 2v i sb standby supply power down mode csi >v cc ?3 v (note 2) 5 15 a current sleep mode csi >v cc ?3 v (note 3) 1 5 ? i li input leakage current v ss < v in < v cc ? ?1 1 a i lo output leakage current 0.45 < v in < v cc ?0 5 10 ? zpld_turbo = off, see i sb ? i cc (dc) operating f = 0 mhz (note 4) (note 5) supply current zpld only zpld_turbo = on, f = 0 mhz 200 400 ?/pt zpld ac base (note 4) see 2.0 ma/mhz fig 38c cmiser = on eprom ac adder (8-bit bus mode) 0.4 1.0 ma/mhz i cc (ac) all other cases 0.9 1.7 ma/mhz (note 5) cmiser = on and 0.7 1.3 ma/mhz 8-bit bus mode sram ac adder cmiser = on and 1 2 ma/mhz 16-bit bus mode cmiser = off 1.9 3.8 ma/mhz 13.9 dc characteristics (zpsd4xxv versions) (3.0 v 10% versions) notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal pd is active. 3. sleep mode bit is set and internal pd is active. 4. see zpld icc/frequency power consumption graph for details. 5. i out = 0 ma. obsolete product(s) - obsolete product(s) psd4xx family 89 -20 -25 zpld_turbo symbol parameter conditions min max min max off * unit i/o input or feedback to t pd combinatorial output port b, e 55 80 add 20 ns t rpd registered input to (note 1) 55 85 add 20 ns combinatorial output t ea input to output enable any input 50 80 add 20 ns t er input to output disable any input 50 80 add 20 ns t arp register clear or preset delay any input 55 80 add 20 ns t arpw register clear or preset any input 30 60 ns pulse width t ard array delay 33 35 ns combinatorial delays (3.0 v 10%) 13.10 ac/dc parameters ? zpld timing parameters (zpsd4xxv versions) (3.0 v 10%) note: 1. port a and latched address from adio (a0, a1, a8 ?a15). -20 -25 zpld_turbo symbol parameter conditions min max min max off * unit maximum frequency external feedback 1/(t s + t co ) 28.57 11.11 mhz maximum frequency f max internal feedback (f cnt ) 1/(t s +t co ?0) 17.24 12.50 mhz maximum frequency pipelined data 1/(t ch + t cl ) 31.25 18.52 mhz t s input setup time any input 45 60 add 20 ns t h input hold time any input 0 0 0 ns t ch clock high time clock input 16 27 0 ns t cl clock low time clock input 16 27 0 ns t co clock to output delay clock input 30 33 0 ns t ard array delay for product term expansion any macrocell 24 35 0 ns t min minimum clock period t ch + t cl 30 30 0 ns synchronous clock mode (3.0 v 10%) * note: if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 20 ns to the timing parameters. obsolete product(s) - obsolete product(s) psd4xx family 90 -20 -25 zpld_turbo symbol parameter conditions min max min max off * unit maximum frequency external feedback 1/(t sa + t coa ) 14.49 11.11 mhz maximum frequency 1/(t sa +t co a ?0) 16.95 12.50 mhz f maxa internal feedback (f cnta ) (note 1) maximum frequency pipelined data 1/(t ch + t cl ) 31.25 18.52 mhz t sa input setup time any input 13 30 add 20 ns t ha input hold time any input 13 30 0 ns t cha clock high time any input 25 27 0 ns t cla clock low time any input 16 27 0 ns t coa clock to output delay any input to port b 56 60 add 20 ns t ard array delay for product term expansion any macrocell 33 35 0 ns t mina minimum clock period 1/f cnt 59 80 0 ns asynchronous clock mode (3.0 v 10%, note 1) ac/dc parameters ? zpld timing parameters (zpsd4xxv versions) (3.0 v 10%) note: 1. only port b has asynchronous outputs. clock into macrocell flip flop is generated by a product term. * if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 20 ns to the timing parameters. obsolete product(s) - obsolete product(s) psd4xx family 91 -20 -25 eprom_cmiser symbol parameter conditions min max min max on unit t lvlx ale or as pulse width 30 30 0 ns t avlx address setup time (note 3) 12 15 0 ns t lxax address hold time (note 3) 12 17 0 ns t avqv address valid to data valid (note 3) 200 250 add 20 ns t slqv cs valid to data valid 200 275 add 20 ns rd to data valid 8/16-bit bus (note 1) 50 80 0 ns t rlqv rd to data valid 8-bit bus, 8031 separate mode (note 2) 57 90 0 ns t rhqx rd data hold time (note 1) 0 0 0 ns t rlrh rd pulse width (note 1) 40 70 0 ns t rhqz rd to data high-z (note 1) 45 45 0 ns t ehel e pulse width 40 70 0 ns t theh r/w setup time to enable 20 15 0 ns t eltl r/w hold time after enable 0 0 0 ns in 16-bit data bus address input valid to mode (note 4) 40 60 0 ns t avpv address output delay in 8-bit data bus 50 60 0 ns mode (note 4) read timing (3.0 v 10%) explanation of ac symbols for non zpld timing. example: t avlx time from address valid to ale invalid. a address l logic level low or ale t r/w c power down n reset t time d input data p port signal v valid e ? q output data x no longer a valid logic level h logic level high r wr, uds, lds, ds, iord, psen z float i interrupt s chip select 13.11 microcontroller interface ?ac/dc parameters (zpsd4xxv versions) (3.0 v 10%) notes: 1. rd timing has the same timing as psen, ds, lds, uds signals. 2. rd and psen have the same timing for 8031 mode. 3. any input used to select an internal psd4xx function. 4. in multiplexed mode latched address generated from adio delay to address output on any port. obsolete product(s) - obsolete product(s) psd4xx family 92 -20 -25 eprom_cmiser symbol parameter conditions min max min max on unit t lvlx ale or as pulse width 30 30 ns t avlx address setup time (note 1) 12 15 ns t lxax address hold time (note 1) 12 17 ns t avwl address valid to leading edge of wr (notes 1 and 3) 35 50 ns t slwl cs valid to leading edge of wr (note 3) 40 60 ns t dvwh wr data setup time (note 3) 25 35 ns t whdx wr data hold time (note 3) 5 10 ns t wlwh wr pulse width (note 3) 30 30 ns t whax trailing edge of wr to address invalid (note 3) 0 0 ns t whpv trailing edge of wr to port output valid (note 3) 50 60 ns in 16-bit data bus 40 60 ns address input valid to mode (note 2) t avpv address output delay in 8-bit data bus 50 60 ns mode (note 2) write timing (3.0 v 10%) microcontroller interface ? ac/dc parameters (zpsd4xxv versions) (3.0 v 10%) notes: 1. any input used to select an internal psd4xx function. 2. in multiplexed mode latched address generated from adio delay to address output on any port. 3. wr timing has the same timing as e, ds, lds, uds, wrl, wrh signals. obsolete product(s) - obsolete product(s) psd4xx family 93 -20 -25 zpld_turbo symbol parameter conditions min max min max off unit t avqv (pa) address valid to data valid (note 3) 95 120 add 20 ns t slqv (pa) cs valid to data valid 100 120 add 20 ns t rlqv (pa) rd to data valid (notes 1 and 4) 50 90 0 ns t dvqv (pa) data in to data out valid 35 50 0 ns t qxrh (pa) rd data hold time (note 1) 0 0 0 ns t rlrh (pa) rd pulse width (note 1) 40 70 0 ns t rhqz (pa) rd to data high-z (note 1) 35 60 0 ns -20 -25 zpld_turbo symbol parameter conditions min max min max off unit t wlqv (pa) wr to data propagation delay (note 2) 60 60 0 ns t dvqv (pa) data to port a data propagation delay (note 5) 40 50 0 ns t whqz (pa) wr invalid to port a tri-state (note 2) 35 60 0 ns port a peripheral data mode read timing (3.0 v 10%) port a peripheral data mode write timing (3.0 v 10%) microcontroller interface ? ac/dc parameters (zpsd4xxv versions) (3.0 v 10%) notes: 1. rd timing has the same timing as psen, ds, lds, uds signals. 2. wr timing has the same timing as e, ds, lds, uds, wrl, wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. obsolete product(s) - obsolete product(s) psd4xx family 94 -20 -25 zpld_turbo symbol parameter conditions min max min max off unit t lvdv ale access time from power down 170 250 add 20 ns t lvdv1 ale or csi access time from sleep 200 250 0 ns t lvdv2 zpld propagation delay in sleep mode 600 900 0 ns t lvdv3 zpld recovery time after sleep mode 250 400 0 ns t chcl apd clock high time using pe7 16 27 0 ns t clch apd clock low time using pe7 16 27 0 ns f max apd maximum frequency using pe7 20.00 18.52 0 mhz t 1 reset active low time 300 400 0 ns t 2 reset high to operational device 300 400 0 ns power down and reset timing (3.0 v 10%) microcontroller interface ? ac/dc parameters (3.0 v 10%) obsolete product(s) - obsolete product(s) psd4xx family 95 figure 39. read timing t avlx t lxax t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out read timing ale /as a /d (bhe) multiplexed bus address (bhe/siz0) non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) (lds, uds) e r/w 14.0 timing diagrams obsolete product(s) - obsolete product(s) psd4xx family 96 figure 40. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale/as a /d (bhe) multiplexed bus address (bhe, siz0) non-multiplexed bus data non-multiplexed bus csi wr (wrh, wrl) (lds, uds) (ds) e r/ w obsolete product(s) - obsolete product(s) psd4xx family 97 figure 42. peripheral i/o write timing figure 41. peripheral i/o read timing t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address data valid ale /as a /d bus rd data on port a csi tdvqv (pa) twlqv (pa) twhqz (pa) address data out a /d bus wr port a data out ale /as obsolete product(s) - obsolete product(s) psd4xx family 98 figure 43. combinatorial timing ? zpld tpd trpd input (from port a) any output any output input (from port b, c, d, e) obsolete product(s) - obsolete product(s) psd4xx family 99 figure 44. synchronous clock mode timing ? zpld figure 45. asynchronous clock mode timing (product-term clock, pb macrocell only) t ch t cl t co t h t s clkin input registered output tcha tcla tcoa tha tsa clock input registered output obsolete product(s) - obsolete product(s) psd4xx family 100 figure 46. input to output disable / enable figure 47. asynchronous reset /preset ter tea input input to output enable/disable tarp register output tarpw reset/preset input obsolete product(s) - obsolete product(s) psd4xx family 101 figure 48. reset timing figure 49. key to switching waveforms t1 t2 waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state obsolete product(s) - obsolete product(s) psd4xx family 102 symbol parameter 14 conditions typical 15 max unit c in capacitance (for input pins only) v in = 0 v 4 6 pf c out capacitance (for input/output pins) v out = 0 v 8 12 pf c vpp capacitance (for wr/v pp or r/w/v pp )v pp = 0 v 18 25 pf notes: 14. these parameters are only sampled and are not 100% tested. 15. typical values are for t a = 25? and nominal supply voltages. t a = 25 ?, f = 1 mhz 15.0 pin capacitance 16.0 ac testing figure 51. ac testing load circuit 17.0 erasure and programming 3.0v 0v test point 1.5v device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance) to clear all locations of their programmed contents, expose the window packaged device to an ultra-violet light source. a dosage of 30 w second/cm 2 is required (40 w second/cm 2 for zpsd4xxv versions). this dosage can be obtained with exposure to a wavelength of 2537 ? and intensity of 12000 ?/cm 2 for 40 to 45 minutes (55 to 60 minutes for zpsd4xxv versions). the device should be about 1 inch from the source, and all filters should be removed from the uv light source prior to erasure. the psd4xx and similar devices will erase with light sources having wavelengths shorter than 4000 ?. although the erasure times will be much longer than with uv sources at 2537 ?, exposure to fluorescent light and sunlight eventually erases the device. for maximum system reliability, these sources should be avoided. if used in such an environment, the package windows should be covered by an opaque substance. upon delivery from st , or after each erasure, the psd4xx device has all bits in the pad and eprom in the ??or high state. the configuration bits are in the ??or low state. the code, configuration, and pad map data are loaded through the procedure of programming information for programming the device is available directly from st . please contact your local sales representative. figure 50. ac testing input/output waveform obsolete product(s) - obsolete product(s) psd4xx family 103 68-pin 68-pin pin no. pldcc/cldcc pin no. pldcc/cldcc package package 1 gnd 35 gnd 2 adio_7 36 pe2 3 adio_6 37 pe1 4 adio_5 38 pe0 5 adio_4 39 csi 6 adio_3 40 reset 7 adio_2 41 rd 8 adio_1 42 clkin 9 adio_0 43 pb7 10 pc7 44 pb6 11 pc6 45 pb5 12 pc5 46 pb4 13 pc4 47 pb3 14 pc3 48 pb2 15 pc2 49 pb1 16 pc1 50 pb0 17 pc0 51 gnd 18 vcc 52 vcc 19 gnd 53 pd7 20 pa7 54 pd6 21 pa6 55 pd5 22 pa5 56 pd4 23 pa4 57 pd3 24 pa3 58 pd2 25 pa2 59 pd1 26 pa1 60 pd0 27 pa0 61 adio_15 28 vstdby 62 adio_14 29 wr 63 adio_13 30 pe7 64 adio_12 31 pe6 65 adio_11 32 pe5 66 adio_10 33 pe4 67 adio_9 34 pe3 68 adio_8 18.0 psd4xx pin assignments obsolete product(s) - obsolete product(s) psd4xx family 104 80-pin 80-pin pin no. tqfp pin no. tqfp package package 1 pc7 41 pb7 2 pc6 42 pb6 3 pc5 43 pb5 4 pc4 44 pb4 5 pc3 45 pb3 6 pc2 46 pb2 7 pc1 47 pb1 8 pc0 48 pb0 9v cc 49 gnd 10 v cc 59 gnd 11 gnd 51 v cc 12 gnd 52 v cc 13 pa7 53 pd7 14 pa6 54 pd6 15 pa5 55 pd5 16 pa4 56 pd4 17 pa3 57 pd3 18 pa2 58 pd2 19 pa1 59 pd1 20 pa0 60 pd0 21 nc 61 nc 22 nc 62 adio_15 23 vstdby 63 adio_14 24 wr 64 adio_13 25 pe7 65 adio_12 26 pe6 66 adio_11 27 pe5 67 adio_10 28 pe4 68 adio_9 29 pe3 69 adio_8 30 gnd 70 gnd 31 gnd 71 gnd 32 pe2 72 adio_7 33 pe1 73 adio_6 34 pe0 74 adio_5 35 csi 75 adio_4 36 reset 76 adio_3 37 rd 77 adio_2 38 clkin 78 adio_1 39 nc 79 adio_0 40 nc 80 nc psd4xx pin assignments obsolete product(s) - obsolete product(s) psd4xx family 105 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 98765432 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7 figure 53. drawing l5 68-pin ceramic leaded chip carrier (cldcc) with window (package type l) 19.0 package information figure 52. drawing j5 68-pin plastic leaded chip carrier (pldcc) (package type j) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 98765432 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7 obsolete product(s) - obsolete product(s) psd4xx family 106 60 pd0 59 pd1 58 pd2 57 pd3 56 pd4 55 pd5 54 pd6 53 pd7 52 v cc 51 v cc 50 gnd 49 gnd 48 pb0 47 pb1 46 pb2 45 pb3 44 pb4 43 pb5 42 pb6 41 pb7 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc v cc gnd gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 54 63 62 61 n/c adio? adio? adio? adio? adio? adio? adio? adio? gnd gnd adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 n/c 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 n/c n/c vstdby wr pe7 pe6 pe5 pe4 pe3 gnd gnd pe2 pe1 pe0 csi reset rd clkin n/c n/c figure 54. drawing u2 80-pin plastic thin quad flatpack (tqfp) (package type u) (top view) obsolete product(s) - obsolete product(s) psd4xx family 107 family: plastic leaded chip carrier millimeters inches symbol min max notes min max notes a 4.19 4.57 0.165 0.180 a1 2.41 3.00 0.095 0.118 a2 3.71 3.91 0.146 0.154 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 c 0.196 0.262 0.0077 0.0083 d 25.02 25.27 0.985 0.995 d1 24.13 24.23 0.950 0.954 d2 22.61 23.62 0.890 0.930 d3 20.32 reference 0.800 reference e 25.02 25.27 0.985 0.995 e1 24.13 24.23 0.950 0.954 e2 22.61 23.62 0.890 0.930 e3 20.32 reference 0.800 reference e1 1.27 reference 0.050 reference n68 68 030195r6 drawing j5 ? 68-pin plastic leaded chip carrier (pldcc) (package type j) b1 a1 a2 e1 e a d d1 68 1 2 3 e3 e2 e1 b d3 d2 c obsolete product(s) - obsolete product(s) psd4xx family 108 family: ceramic leaded chip carrier ? cerquad millimeters inches symbol min max notes min max notes a 3.94 4.57 0.155 0.180 a1 2.29 2.92 0.090 0.115 a2 3.05 3.68 0.120 0.145 b 0.43 0.53 0.017 0.021 b1 0.66 0.81 0.026 0.032 c 0.15 0.25 0.006 0.010 d 25.02 25.27 0.985 0.995 d1 23.93 24.28 0.942 0.956 d2 22.35 23.88 0.880 0.940 d3 20.32 reference 0.800 reference e 25.02 25.27 0.985 0.995 e1 23.93 24.28 0.942 0.956 e2 22.35 23.88 0.880 0.940 e3 20.32 reference 0.800 reference e1 1.27 reference 0.050 reference n68 68 030195r6 drawing l5 ? 68-pin pocketed ceramic leaded chip carrier (cldcc) ? cerquad (package type l) d3 b1 b a1 a e1 e 68 d2 a2 c 1 2 3 d1 d e3 e1 to reduce lead damage, lead tips reside in pockets on the bottom of the package. view a view a e2 obsolete product(s) - obsolete product(s) psd4xx family 109 drawing u2 ? 80-pin plastic thin quad flatpack (tqfp) (package type u) d d1 d3 e3 e1 e index mark standoff: 0.05 mm min. load coplanarity: 0.102 mm max. l c be1 a2 a a1 a 80 1 2 3 family: plastic thin quad flatpack (tqfp) millimeters inches symbol min max notes min max notes a 0 8 0 8 a 1.60 0.063 a1 0.54 0.74 0.021 0.029 a2 1.15 1.55 0.045 0.061 b 0.30 reference 0.012 reference c 0.09 0.20 0.004 0.008 d 15.75 16.25 0.620 0.640 d1 13.90 14.10 0.547 0.555 d3 12.35 reference 0.486 reference e 15.75 16.25 0.620 0.640 e1 13.90 14.10 0.547 0.555 e3 12.35 reference 0.486 reference e1 0.65 reference 0.026 reference l 0.35 0.75 0.014 0.030 n80 80 030195r1 obsolete product(s) - obsolete product(s) psd4xx family 110 part # mcu plds/decoders i/o memory other psd zpsd zpsdv data path inputs ports eprom sram four 16-bit timer/counters interface product terms (w/bb) watchdog (16-bit) input micro ? cells inter. contr. output micro ? cells periph. mode outputs security page apd reg. psd411a1 zpsd411a1 zpsd411a1v 8 plus1 37 113 8 16 x 40 256kb 16kb x x x psd401a1 zpsd401a1 zpsd401a1v 16/8 plus1 37 113 8 16 x 40 256kb 16kb x x x zpsd412a0 8 plus1 37 113 8 16 x 40 512kb 16kb x x x psd412a1 zpsd412a1 zpsd412a1v 8 plus1 37 113 8 16 x 40 512kb 16kb x x x psd402a1 zpsd402a1 zpsd402a1v 16/8 plus1 37 113 8 16 x 40 512kb 16kb x x x psd413a1 zpsd413a1 zpsd413a1v 8 plus1 37 113 8 16 x 40 1024kb 16kb x x x psd403a1 zpsd403a1 zpsd403a1v 16/8 plus1 37 113 8 16 x 40 1024kb 16kb x x x psd411a2 zpsd411a2 zpsd411a2v 8 plus1 59 126 24 24 x 40 256kb 16kb x x x psd401a2 zpsd401a2 zpsd401a2v 16/8 plus1 59 126 24 24 x 40 256kb 16kb x x x psd412a2 zpsd412a2 zpsd412a2v 8 plus1 59 126 24 24 x 40 512kb 16kb x x x psd402a2 zpsd402a2 zpsd402a2v 16/8 plus1 59 126 24 24 x 40 512kb 16kb x x x psd413a2 zpsd413a2 zpsd413a2v 8 plus1 59 126 24 24 x 40 1024kb 16kb x x x psd403a2 zpsd403a2 zpsd403a2v 16/8 plus1 59 126 24 24 x 40 1024kb 16kb x x x 20.1 psd4xx family ? selector guide 20.0 psd4xx product ordering information obsolete product(s) - obsolete product(s) - obsolet psd4xx family 111 psd4xx product ordering information (cont.) temperature (blank = commercial, i = industrial, m = military) package type speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) revision (blank = no revision) supply voltage (blank = 5v, v = 3 volt) base part number - see selector guide psd ( st programmable system device) fam. power down feature (blank = standard, z = zero power feature) z psd -a -20 j i 413a2 v 20.2 part number construction operating speed temperature part number (ns) package type range psd401a1-c-70j 70 68 pin pldcc comm? psd401a1-c-70l 70 68 pin cldcc comm? psd401a1-c-70u 70 68 pin tqfp comm? psd401a1-c-90ji 90 68 pin pldcc industrial psd401a1-c-90ui 90 68 pin tqfp industrial psd401a1-c-12j 120 68 pin pldcc comm? psd401a1-c-15j 150 68 pin pldcc comm? psd401a1-c-15l 150 68 pin cldcc comm? psd401a1-c-15u 150 68 pin tqfp comm? psd401a2-c-70j 70 68 pin pldcc comm? psd401a2-c-70l 70 68 pin cldcc comm? psd401a2-c-70u 70 68 pin tqfp comm? psd401a2-c-90ji 90 68 pin pldcc industrial psd401a2-c-90ui 90 68 pin tqfp industrial psd401a2-c-15j 150 68 pin pldcc comm? psd401a2-c-15l 150 68 pin cldcc comm? psd401a2-c-15u 150 68 pin tqfp comm? 20.3 ordering information obsolete product(s) - obsolete product(s) psd4xx family 112 operating speed temperature part number (ns) package type range psd402a1-c-70j 70 68 pin pldcc comm? psd402a1-c-70l 70 68 pin cldcc comm? psd402a1-c-70u 70 68 pin tqfp comm? psd402a1-c-90ji 90 68 pin pldcc industrial psd402a1-c-90ui 90 68 pin tqfp industrial psd402a1-c-15j 150 68 pin pldcc comm? psd402a1-c-15l 150 68 pin cldcc comm? psd402a1-c-15u 150 68 pin tqfp comm? psd402a2-c-70j 70 68 pin pldcc comm? psd402a2-c-70l 70 68 pin cldcc comm? psd402a2-c-70u 70 68 pin tqfp comm? psd402a2-c-90ji 90 68 pin pldcc industrial psd402a2-c-90ui 90 68 pin tqfp industrial psd402a2-c-15j 150 68 pin pldcc comm? psd402a2-c-15l 150 68 pin cldcc comm? psd402a2-c-15u 150 68 pin tqfp comm? psd403a1-c-70j 70 68 pin pldcc comm? psd403a1-c-70l 70 68 pin cldcc comm? psd403a1-c-70u 70 68 pin tqfp comm? psd403a1-c-90ji 90 68 pin pldcc industrial psd403a1-c-90ui 90 68 pin tqfp industrial psd403a1-c-15j 150 68 pin pldcc comm? psd403a1-c-15l 150 68 pin cldcc comm? psd403a1-c-15u 150 68 pin tqfp comm? psd403a2-c-70j 70 68 pin pldcc comm? psd403a2-c-70l 70 68 pin cldcc comm? psd403a2-c-70u 70 68 pin tqfp comm? psd403a2-c-90ji 90 68 pin pldcc industrial psd403a2-c-90ui 90 68 pin tqfp industrial psd403a2-c-15j 150 68 pin pldcc comm? psd403a2-c-15l 150 68 pin cldcc comm? psd403a2-c-15u 150 68 pin tqfp comm? PSD411A1-C-70J 70 68 pin pldcc comm? psd411a1-c-70l 70 68 pin cldcc comm? psd411a1-c-70u 70 68 pin tqfp comm? psd411a1-c-90ji 90 68 pin pldcc industrial psd411a1-c-90ui 90 68 pin tqfp industrial psd411a1-c-15j 150 68 pin pldcc comm? psd411a1-c-15l 150 68 pin cldcc comm? psd411a1-c-15u 150 68 pin tqfp comm? ordering information psd4xx product ordering information (cont.) obsolete product(s) - obsolete product(s) psd4xx family 113 operating speed temperature part number (ns) package type range psd411a2-c-70j 70 68 pin pldcc comm? psd411a2-c-70l 70 68 pin cldcc comm? psd411a2-c-70u 70 68 pin tqfp comm? psd411a2-c-90ji 90 68 pin pldcc industrial psd411a2-c-90ui 90 68 pin tqfp industrial psd411a2-c-15j 150 68 pin pldcc comm? psd411a2-c-15l 150 68 pin cldcc comm? psd411a2-c-15u 150 68 pin tqfp comm? psd412a1-c-70j 70 68 pin pldcc comm? psd412a1-c-70l 70 68 pin cldcc comm? psd412a1-c-70u 70 68 pin tqfp comm? psd412a1-c-90ji 90 68 pin pldcc industrial psd412a1-c-90ui 90 68 pin tqfp industrial psd412a1-c-15j 150 68 pin pldcc comm? psd412a1-c-15l 150 68 pin cldcc comm? psd412a1-c-15u 150 68 pin tqfp comm? psd412a2-c-70j 70 68 pin pldcc comm? psd412a2-c-70l 70 68 pin cldcc comm? psd412a2-c-70u 70 68 pin tqfp comm? psd412a2-c-90ji 90 68 pin pldcc industrial psd412a2-c-90ui 90 68 pin tqfp industrial psd412a2-c-15j 150 68 pin pldcc comm? psd412a2-c-15l 150 68 pin cldcc comm? psd412a2-c-15u 150 68 pin tqfp comm? psd413a1-c-70j 70 68 pin pldcc comm? psd413a1-c-70l 70 68 pin cldcc comm? psd413a1-c-70u 70 68 pin tqfp comm? psd413a1-c-90ji 90 68 pin pldcc industrial psd413a1-c-90ui 90 68 pin tqfp industrial psd413a1-c-15j 150 68 pin pldcc comm? psd413a1-c-15l 150 68 pin cldcc comm? psd413a1-c-15u 150 68 pin tqfp comm? psd413a2-c-70j 70 68 pin pldcc comm? psd413a2-c-70l 70 68 pin cldcc comm? psd413a2-c-70u 70 68 pin tqfp comm? psd413a2-c-90ji 90 68 pin pldcc industrial psd413a2-c-90ui 90 68 pin tqfp industrial psd413a2-c-15j 150 68 pin pldcc comm? psd413a2-c-15l 150 68 pin cldcc comm? psd413a2-c-15u 150 68 pin tqfp comm? ordering information psd4xx product ordering information (cont.) obsolete product(s) - obsolete product(s) psd4xx family 114 operating speed temperature part number (ns) package type range zpsd401a1-c-70j 70 68 pin pldcc comm? zpsd401a1-c-70l 70 68 pin cldcc comm? zpsd401a1-c-70u 70 80 pin tqfp comm? zpsd401a1-c-90ji 90 68 pin pldcc industrial zpsd401a1-c-90ui 90 80 pin tqfp industrial zpsd401a1-c-15j 150 68 pin pldcc comm? zpsd401a1-c-15l 150 68 pin cldcc comm? zpsd401a1-c-15u 150 80 pin tqfp comm? zpsd401a1v-c-20j 200 68 pin pldcc comm? zpsd401a1v-c-20ji 200 68 pin pldcc industrial zpsd401a1v-c-20l 200 68 pin cldcc comm? zpsd401a1v-c-20u 200 80 pin tqfp comm? zpsd401a1v-c-20ui 200 80 pin tqfp industrial zpsd401a1v-c-25j 250 68 pin pldcc comm? zpsd401a1v-c-25l 250 68 pin cldcc comm? zpsd401a1v-c-25u 250 80 pin tqfp comm? zpsd401a2-c-70j 70 68 pin pldcc comm? zpsd401a2-c-70l 70 68 pin cldcc comm? zpsd401a2-c-70u 70 80 pin tqfp comm? zpsd401a2-c-90ji 90 68 pin pldcc industrial zpsd401a2-c-90ui 90 80 pin tqfp industrial zpsd401a2-c-15j 150 68 pin pldcc comm? zpsd401a2-c-15l 150 68 pin cldcc comm? zpsd401a2-c-15u 150 80 pin tqfp comm? zpsd401a2v-c-20j 200 68 pin pldcc comm? zpsd401a2v-c-20ji 200 68 pin pldcc industrial zpsd401a2v-c-20l 200 68 pin cldcc comm? zpsd401a2v-c-20u 200 80 pin tqfp comm? zpsd401a2v-c-20ui 200 80 pin tqfp industrial zpsd401a2v-c-25j 250 68 pin pldcc comm? zpsd401a2v-c-25l 250 68 pin cldcc comm? zpsd401a2v-c-25u 250 80 pin tqfp comm? zpsd402a1-c-70j 70 68 pin pldcc comm? zpsd402a1-c-70l 70 68 pin cldcc comm? zpsd402a1-c-70u 70 80 pin tqfp comm? zpsd402a1-c-90ji 90 68 pin pldcc industrial zpsd402a1-c-90ui 90 80 pin tqfp industrial zpsd402a1-c-15j 150 68 pin pldcc comm? zpsd402a1-c-15l 150 68 pin cldcc comm? zpsd402a1-c-15u 150 80 pin tqfp comm? ordering information psd4xx product ordering information (cont.) obsolete product(s) - obsolete product(s) psd4xx family 115 operating speed temperature part number (ns) package type range zpsd402a1v-c-20j 200 68 pin pldcc comm? zpsd402a1v-c-20ji 200 68 pin pldcc industrial zpsd402a1v-c-20l 200 68 pin cldcc comm? zpsd402a1v-c-20u 200 80 pin tqfp comm? zpsd402a1v-c-20ui 200 80 pin tqfp industrial zpsd402a1v-c-25j 250 68 pin pldcc comm? zpsd402a1v-c-25l 250 68 pin cldcc comm? zpsd402a1v-c-25u 250 80 pin tqfp comm? zpsd402a2-c-70j 70 68 pin pldcc comm? zpsd402a2-c-70l 70 68 pin cldcc comm? zpsd402a2-c-70u 70 80 pin tqfp comm? zpsd402a2-c-90ji 90 68 pin pldcc industrial zpsd402a2-c-90ui 90 80 pin tqfp industrial zpsd402a2-c-15j 150 68 pin pldcc comm? zpsd402a2-c-15l 150 68 pin cldcc comm? zpsd402a2-c-15u 150 80 pin tqfp comm? zpsd402a2v-c-20j 200 68 pin pldcc comm? zpsd402a2v-c-20ji 200 68 pin pldcc industrial zpsd402a2v-c-20l 200 68 pin cldcc comm? zpsd402a2v-c-20u 200 80 pin tqfp comm? zpsd402a2v-c-20ui 200 80 pin tqfp industrial zpsd402a2v-c-25j 250 68 pin pldcc comm? zpsd402a2v-c-25l 250 68 pin cldcc comm? zpsd402a2v-c-25u 250 80 pin tqfp comm? zpsd403a1-c-70j 70 68 pin pldcc comm? zpsd403a1-c-70l 70 68 pin cldcc comm? zpsd403a1-c-70u 70 80 pin tqfp comm? zpsd403a1-c-90ji 90 68 pin pldcc industrial zpsd403a1-c-90ui 90 80 pin tqfp industrial zpsd403a1-c-15j 150 68 pin pldcc comm? zpsd403a1-c-15l 150 68 pin cldcc comm? zpsd403a1-c-15u 150 80 pin tqfp comm? zpsd403a1v-c-20j 200 68 pin pldcc comm? zpsd403a1v-c-20ji 200 68 pin pldcc industrial zpsd403a1v-c-20l 200 68 pin cldcc comm? zpsd403a1v-c-20u 200 80 pin tqfp comm? zpsd403a1v-c-20ui 200 80 pin tqfp industrial zpsd403a1v-c-25j 250 68 pin pldcc comm? zpsd403a1v-c-25l 250 68 pin cldcc comm? zpsd403a1v-c-25u 250 80 pin tqfp comm? ordering information psd4xx product ordering information (cont.) obsolete product(s) - obsolete product(s) psd4xx family 116 operating speed temperature part number (ns) package type range zpsd403a2-c-70j 70 68 pin pldcc comm? zpsd403a2-c-70l 70 68 pin cldcc comm? zpsd403a2-c-70u 70 80 pin tqfp comm? zpsd403a2-c-90ji 90 68 pin pldcc industrial zpsd403a2-c-90li 90 68 pin cldcc industrial zpsd403a2-c-90ui 90 80 pin tqfp industrial zpsd403a2-c-15j 150 68 pin pldcc comm? zpsd403a2-c-15l 150 68 pin cldcc comm? zpsd403a2-c-15u 150 80 pin tqfp comm? zpsd403a2v-c-20j 200 68 pin pldcc comm? zpsd403a2v-c-20ji 200 68 pin pldcc industrial zpsd403a2v-c-20l 200 68 pin cldcc comm? zpsd403a2v-c-20u 200 80 pin tqfp comm? zpsd403a2v-c-20ui 200 80 pin tqfp industrial zpsd403a2v-c-25j 250 68 pin pldcc comm? zpsd403a2v-c-25l 250 68 pin cldcc comm? zpsd403a2v-c-25u 250 80 pin tqfp comm? zPSD411A1-C-70J 70 68 pin pldcc comm? zpsd411a1-c-70l 70 68 pin cldcc comm? zpsd411a1-c-70u 70 80 pin tqfp comm? zpsd411a1-c-90ji 90 68 pin pldcc industrial zpsd411a1-c-90ui 90 80 pin tqfp industrial zpsd411a1-c-15j 150 68 pin pldcc comm? zpsd411a1-c-15l 150 68 pin cldcc comm? zpsd411a1-c-15u 150 80 pin tqfp comm? zpsd411a1v-c-20j 200 68 pin pldcc comm? zpsd411a1v-c-20ji 200 68 pin pldcc industrial zpsd411a1v-c-20l 200 68 pin cldcc comm? zpsd411a1v-c-20u 200 80 pin tqfp comm? zpsd411a1v-c-20ui 200 80 pin tqfp industrial zpsd411a1v-c-25j 250 68 pin pldcc comm? zpsd411a1v-c-25l 250 68 pin cldcc comm? zpsd411a1v-c-25u 250 80 pin tqfp comm? zpsd411a2-c-70j 70 68 pin pldcc comm? zpsd411a2-c-70l 70 68 pin cldcc comm? zpsd411a2-c-70u 70 80 pin tqfp comm? zpsd411a2-c-90ji 90 68 pin pldcc industrial zpsd411a2-c-90ui 90 80 pin tqfp industrial zpsd411a2-c-15j 150 68 pin pldcc comm? zpsd411a2-c-15l 150 68 pin cldcc comm? zpsd411a2-c-15u 150 80 pin tqfp comm? ordering information psd4xx product ordering information (cont.) obsolete product(s) - obsolete product(s) psd4xx family 117 operating speed temperature part number (ns) package type range zpsd411a2v-c-20j 200 68 pin pldcc comm? zpsd411a2v-c-20ji 200 68 pin pldcc industrial zpsd411a2v-c-20l 200 68 pin cldcc comm? zpsd411a2v-c-20u 200 80 pin tqfp comm? zpsd411a2v-c-20ui 200 80 pin tqfp industrial zpsd411a2v-c-25j 250 68 pin pldcc comm? zpsd411a2v-c-25l 250 68 pin cldcc comm? zpsd411a2v-c-25u 250 80 pin tqfp comm? zpsd412a0-c-70j 70 68 pin pldcc comm? zpsd412a0-c-70l 70 68 pin cldcc comm? zpsd412a0-c-70u 70 80 pin tqfp comm? zpsd412a0-c-90ji 90 68 pin pldcc industrial zpsd412a0-c-90ui 90 80 pin tqfp industrial zpsd412a0-c-15j 150 68 pin pldcc comm? zpsd412a0-c-15l 150 68 pin cldcc comm? zpsd412a0-c-15u 150 80 pin tqfp comm? zpsd412a1-c-70j 70 68 pin pldcc comm? zpsd412a1-c-70l 70 68 pin cldcc comm? zpsd412a1-c-70u 70 80 pin tqfp comm? zpsd412a1-c-90ji 90 68 pin pldcc industrial zpsd412a1-c-90ui 90 80 pin tqfp industrial zpsd412a1-c-15j 150 68 pin pldcc comm? zpsd412a1-c-15l 150 68 pin cldcc comm? zpsd412a1-c-15u 150 80 pin tqfp comm? zpsd412a1v-c-20j 200 68 pin pldcc comm? zpsd412a1v-c-20ji 200 68 pin pldcc industrial zpsd412a1v-c-20l 200 68 pin cldcc comm? zpsd412a1v-c-20u 200 80 pin tqfp comm? zpsd412a1v-c-20ui 200 80 pin tqfp industrial zpsd412a1v-c-25j 250 68 pin pldcc comm? zpsd412a1v-c-25l 250 68 pin cldcc comm? zpsd412a1v-c-25u 250 80 pin tqfp comm? zpsd412a2-c-70j 70 68 pin pldcc comm? zpsd412a2-c-70l 70 68 pin cldcc comm? zpsd412a2-c-70u 70 80 pin tqfp comm? zpsd412a2-c-90ji 90 68 pin pldcc industrial zpsd412a2-c-90ui 90 80 pin tqfp industrial zpsd412a2-c-15j 150 68 pin pldcc comm? zpsd412a2-c-15l 150 68 pin cldcc comm? zpsd412a2-c-15u 150 80 pin tqfp comm? ordering information psd4xx product ordering information (cont.) obsolete product(s) - obsolete product(s) psd4xx family 118 operating speed temperature part number (ns) package type range zpsd412a2v-c-20j 200 68 pin pldcc comm? zpsd412a2v-c-20ji 200 68 pin pldcc industrial zpsd412a2v-c-20l 200 68 pin cldcc comm? zpsd412a2v-c-20u 200 80 pin tqfp comm? zpsd412a2v-c-20ui 200 80 pin tqfp industrial zpsd412a2v-c-25j 250 68 pin pldcc comm? zpsd412a2v-c-25l 250 68 pin cldcc comm? zpsd412a2v-c-25u 250 80 pin tqfp comm? zpsd413a1-c-70j 70 68 pin pldcc comm? zpsd413a1-c-70l 70 68 pin cldcc comm? zpsd413a1-c-70u 70 80 pin tqfp comm? zpsd413a1-c-90ji 90 68 pin pldcc industrial zpsd413a1-c-90ui 90 80 pin tqfp industrial zpsd413a1-c-15j 150 68 pin pldcc comm? zpsd413a1-c-15l 150 68 pin cldcc comm? zpsd413a1-c-15u 150 80 pin tqfp comm? zpsd413a1v-c-20j 200 68 pin pldcc comm? zpsd413a1v-c-20ji 200 68 pin pldcc industrial zpsd413a1v-c-20l 200 68 pin cldcc comm? zpsd413a1v-c-20u 200 80 pin tqfp comm? zpsd413a1v-c-20ui 200 80 pin tqfp industrial zpsd413a1v-c-25j 250 68 pin pldcc comm? zpsd413a1v-c-25l 250 68 pin cldcc comm? zpsd413a1v-c-25u 250 80 pin tqfp comm? zpsd413a2-c-70j 70 68 pin pldcc comm? zpsd413a2-c-70l 70 68 pin cldcc comm? zpsd413a2-c-70u 70 80 pin tqfp comm? zpsd413a2-c-90ji 90 68 pin pldcc industrial zpsd413a2-c-90ui 90 80 pin tqfp industrial zpsd413a2-c-15j 150 68 pin pldcc comm? zpsd413a2-c-15l 150 68 pin cldcc comm? zpsd413a2-c-15u 150 80 pin tqfp comm? zpsd413a2v-c-20j 200 68 pin pldcc comm? zpsd413a2v-c-20ji 200 68 pin pldcc industrial zpsd413a2v-c-20l 200 68 pin cldcc comm? zpsd413a2v-c-20u 200 80 pin tqfp comm? zpsd413a2v-c-20ui 200 80 pin tqfp industrial zpsd413a2v-c-25j 250 68 pin pldcc comm? zpsd413a2v-c-25l 250 68 pin cldcc comm? zpsd413a2v-c-25u 250 80 pin tqfp comm? ordering information psd4xx product ordering information (cont.) obsolete product(s) - obsolete product(s) psd4xx, zpsd4xx 2/3 revision history table 1. document revision history date rev. description of revision jul-1993 1.0 psd4xx: document written in the wsi format. initial release mar-1997 1.1 zpsd4xx: updated specifications may-1998 1.2 psd4xx updated specifications, -12 speed grade removed feb-1999 1.3 february, 1999 psd4xxr, zpsd4xxr combined data sheets, eliminated military parts, eliminated various speed grades, updated specifications. 31-jan-2002 1.4 psd4xx, zpsd4xx: low cost field programmable microcontroller peripherals front page, and back two pages, in st format, added to the pdf file any references to waferscale, wsi, easyflash and psdsoft 2000 updated to st, st, flash+psd and psdsoft express obsolete product(s) - obsolete product(s) 3/3 psd4xx, zpsd4xx information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com obsolete product(s) - obsolete product(s) |
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